Abstract: A semiconductor device (10) is formed on a semiconductor substrate (12) whose surface (24) is formed with a trench (18). A capacitor (20) has a first plate (22) formed over the substrate surface with first and second portions lining first and second sidewalls (25) of the trench, respectively. A second plate (35, 38) is formed over the first plate and extends into the trench between the first and second portions.

Abstract: In one embodiment, a lateral FET structure (30) is formed in a body of semiconductor material (32). The structure (30) includes a plurality non-interdigitated drain regions (39) that are coupled together with a conductive layer (57), and a plurality of source regions (34) that are coupled together with a different conductive layer (51). One or more interlayer dielectrics (53,54) separate the two conductive layers (51,57). The individual source regions (34) are absent small radius fingertip regions.

Abstract: In one embodiment, a transistor is formed to have alternating depletion and conduction regions that are formed by doping the depletion and conduction regions through an opening in a substrate of the transistor.

Abstract: A voltage regulator (10) is formed to generate a compensation current to flow when an output voltage of the voltage regulator (10) exceeds a compensation value. The compensation current is at least equal to the leakage current of the output transistor (24).

Abstract: A variable-frequency oscillator (10) is formed to change an internal delay of the oscillator inversely proportional to changes in the frequency of the oscillator.

Abstract: A power supply system (10) forms an active zone that facilitates the power supply system (10) enabling an output transistor (37) when the input voltage (30) is between a first voltage value and a second voltage value. When the output transistor is enabled, it forms a load current (35) having an instantaneous value that when averaged over the period of the input signal results in a desired average value of the load current.

Abstract: In one embodiment, a power switch device (33) includes a first MOSFET device 41 and a second MOSFET device (42). A split gate structure (84) including a first gate electrode (48,87) controls the first MOSFET device (41). A second gate electrode (49,92) controls the second MOSFET device (42). A current limit device (38) is coupled to the first gate electrode (48,97) to turn on the first MOSFET device during a current limit mode. A comparator device (36) is coupled to the second gate electrode (49,92) to turn on the second MOSFET device (42) when the power switch device (33) is no longer in current limit mode.

Abstract: A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23, 24).

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: A power control system uses two separate currents to control a startup operation of the power control system. One of the currents has a small value and is used to charge an output voltage to an initial value. Once the initial value is reached, a second current that has a large value is used to charge the output voltage to an operating voltage value.

Abstract: An integrated detector circuit (20) includes first and second gain stages (GS1, GS2). The first gain stage has an input (82) that monitors a high frequency signal (VRFDET) for routing a first detection current (IS1) to a node (60). The second gain stage includes a first current source (PF1) that supplies a bias current (IMAX1) indicative of a predefined amplitude of the high frequency signal. An input of the second gain stage monitors the high frequency signal to route a portion of the bias current to the node as a second detection current (IS2), which is limited to the bias current when the high frequency signal is greater than the predefined amplitude to compensate for a nonlinearity in a transconductance of the second gain stage.

Abstract: A differential transistor (10, 25) includes a depletion mode transistor (15,30) that has a source connected to a source of an enhancement mode transistor (11,26). The gates of the depletion mode and enhancement mode transistors are driven differentially.

Abstract: An automatic reel changer (10) for a tape-and-reel handler is formed to automatically insert a carrier tape (15) from the tape-and-reel handler into an empty receiving reel (80), wind the carrier tape (15) onto the receiving reel (80), and apply a securing device to keep the carrier tape (15) fixedly attached to the receiving reel (80). The automatic reel changer (10) then removes the full receiving reel (80) and replaces it with another empty receiving reel (81) and continues the process.

Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.

Abstract: A lead frame with a plurality of bump terminals is provided. Stamping an indentation into each lead in the lead frame forms the bump terminals. The bump terminals will be used as contact points in a completed semiconductor device.

Abstract: A method of making a semiconductor device 10 by forming a first dielectric layer 140 on a substrate, etching through the first dielectric layer to form a trench 150 having a channel region 135 on a sidewall 160 of the trench, and laterally removing a portion of the first dielectric layer adjacent to the sidewall of the trench above the channel region for defining a source region 280 of the semiconductor device.

Abstract: A method of forming a leadframe (10) provides blocking fulcrums (21,23) adjacent to the leads (12,13,14, and 15). During the process of encapsulating the leadframe (10), the blocking fulcrums (21,23) restrict encapsulating material from exiting the mold cavity and from attaching to the leads (12,13,14, and 15).

Abstract: A power supply system includes a non-linear section that provides an intermediate voltage. A linear section receives the intermediate voltage and generates the output voltage. The linear section forms a control signal that is used by the non-linear section to change the value of the intermediate voltage as the output voltage changes to keep the differential voltage across the linear section low.

Abstract: A method of forming medium breakdown voltage vertical transistors (11) and lateral transistors (12, 13) on the same substrate (14) provides for optimizing the epitaxial layer (16) for the lateral transistors (12, 13). The vertical transistor (11) is formed in a well (18) that has a lower resistivity than the epitaxial layer (16) to provide the required low on-resistance for the vertical power transistor (11).

Abstract: In one embodiment, a bipolar cell (31) includes a cell boundary (32) that defines a cell active area (33), a first array of bipolar transistors (41) is formed within the cell active area (33) and configured for a first function. The bipolar transistors (42) within the first array (41) are parallel to each other. The bipolar cell (31) further includes a second array of bipolar transistors (61) formed within the cell active area (33) and configured for a second function that is different than the first function. The bipolar transistors (62) within the second array (61) are parallel to each other and oriented in a different direction than the transistors (42) in the first array (41).