Patents Assigned to Semiconductor Ltd.
  • Publication number: 20240044954
    Abstract: The present application relates to current sensing circuitry (100) that comprises a differential amplifier (110) comprising first and second inputs configured to sense a current across a sense resistance, and an output configured to output a current sense signal. The circuitry (100) further comprises a first current source, a second current source and a switch network operable in: a first phase in which the first current source is connected to the first input and disconnected from the output, and the second current source is connected to the output and disconnected from the first input; and a second phase in which the first current source is connected to the output and disconnected from the first input, and the second current source is connected to the first input and disconnected from the output.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 8, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Dipankar NAG, Peter HSU, Kapil R. SHARMA, Gordon J. BATES, Simon R. FOSTER, Mark J. MCCLOY-STEVENS
  • Publication number: 20240047570
    Abstract: A power semiconductor device includes: a drain electrode; a first conductive substrate disposed on the drain electrode; a first conductive epitaxial layer disposed on the first conductive substrate; a first conductive drift layer formed within the first conductive epitaxial layer; trenches formed in the first conductive epitaxial layer; a shield electrode formed in a lower portion of each trench; a shield oxide layer formed within each trench and formed to surround the shield electrode; a gate electrode formed within each trench and formed on the shield electrode; a second conductive body region formed on an upper portion comprising a surface of the first conductive epitaxial layer between the plurality of trenches; a source region formed on the second conductive body region; an insulation layer formed on the gate electrode; a source contact layer formed in contact with the source region; and a source electrode formed on the source contact layer.
    Type: Application
    Filed: February 15, 2023
    Publication date: February 8, 2024
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Chanho PARK, Hohyun KIM, Youngseok KIM, Taehyun OH
  • Publication number: 20240048903
    Abstract: This disclosure provides techniques for determining a reference resistance of a loudspeaker, such as in a mobile device. The reference resistance value may be used, among other applications, for speaker protection by reducing overdrive of the loudspeaker beyond safe temperature, which could damage the loudspeaker, while allowing driving of the loudspeaker closer to safety limits to improve performance of the loudspeaker. In a first aspect, a method of audio device monitoring includes applying a first signal to a loudspeaker; measuring a voltage and a current for the loudspeaker while applying the first signal to the loudspeaker; and determining a reference resistance for the loudspeaker based on the voltage and the current. Other aspects and features are also claimed and described.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 8, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Sandeep P. Sira, Philip B. J. Clarkin, Roberto Napoli
  • Patent number: 11894299
    Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR LTD
    Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
  • Publication number: 20240040316
    Abstract: In an example there is provided a first integrated circuit. The first integrated circuit is configured to receive an audio signal and configured to drive an audio transducer based on the received audio signal. The first integrated circuit is configured to transmit a portion of the audio signal to a second integrated circuit.
    Type: Application
    Filed: June 16, 2023
    Publication date: February 1, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Jonathan E. EKLUND, Daniel WEBER, Andrew I. BOTHWELL, Robert J. HATFIELD
  • Patent number: 11887892
    Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 30, 2024
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won Jeong, Jang Hee Lee, Young Hun Jun, Jong Woon Lee, Jae Sik Choi
  • Publication number: 20240030923
    Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: John Laurence PENNOCK, John Paul LESSO
  • Publication number: 20240031693
    Abstract: For example, analog pixel circuitry may include a first input to input an analog pixel signal of the pixel; Sample and Hold (SH) circuitry to provide an analog sample of the pixel based on the analog pixel signal; one or more second inputs to input analog samples of one or more binning pixels, respectively; a plurality of capacitors having capacitor outputs connected to a common output terminal, wherein a capacitor input of a first capacitor is connected to an input terminal to input the analog sample of the pixel from the SH circuitry, wherein capacitor inputs of one or more second capacitors are connected to the one or more second inputs, respectively; and an amplifier configured to provide an amplified analog signal by amplifying an analog signal from the common output terminal.
    Type: Application
    Filed: July 24, 2022
    Publication date: January 25, 2024
    Applicant: TOWER SEMICONDUCTOR LTD.
    Inventors: Alexander Faingersh, Vered Antebi, Raz Reshef
  • Publication number: 20240012035
    Abstract: This application relates to methods and apparatus for sensing current in a monitored current path, where the monitored current path is bidirectional such that current can flow in either direction along the monitored current path. A current sensor has first and second sense resistors (401a, 401b) configured to each pass a current corresponding to the current in the monitored current path. The first and second sense resistors are configured to have a matching arrangement, such that current flow through the first sense resistor when current is flowing in one direction in the monitored current path matches current flow through the second sense resistor when current is flowing in the opposite direction in the monitored current path.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 11, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Kapil R. SHARMA, Kathryn R. HOLLAND, Matthew PETHERBRIDGE, Peter HSU, John B. BOWLERWELL
  • Publication number: 20240012140
    Abstract: A method for generating a signal for a device process may include retrieving a reduced-memory template signal centered on a chosen subharmonic of a reconstruction sample rate, upsampling the reduced-memory template signal to generate the signal for the device process at a desired data rate, and communicating the signal to a transducer for playback by the transducer.
    Type: Application
    Filed: June 16, 2023
    Publication date: January 11, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Dana J. TAIPALE, Meena MATAI
  • Patent number: 11863948
    Abstract: An acoustic signal processing system and method includes classification technology to classify a relationship between at least two sound components of a received sound signal. The exemplary sound components are ambient noise and localized noise. The classification technology dynamically determines a classification value that represents the relationship between the sound components and processes the sound signal in accordance with the acoustic signal classification to modify the sound signal. In at least one embodiment, dynamic classification of the relationship between sound components in a sound signal and responsive signal processing improve performance of systems, such as an active noise cancellation (ANC) system, by, for example, attenuating at least one of the sound components and/or enhancing at least one of the sound components. In an ANC system context, the sound components generally include noise components such as ambient noise and noise localized to a microphone.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 2, 2024
    Assignee: Cirrus Logic International Semiconductor Ltd.
    Inventors: Nitin Kwatra, Jeffrey D. Alderson
  • Publication number: 20230421951
    Abstract: Circuitry for acoustic crosstalk cancellation between first and second acoustic signals, the circuitry comprising: crosstalk cancellation circuitry configured to: receive a first audio signal and, based on the received first audio signal, generate a first crosstalk cancellation signal; receive a second audio signal and, based on the received second audio signal, generate a second crosstalk cancellation signal; combine the first crosstalk cancellation signal with a signal indicative of the second audio signal to generate a first crosstalk cancellation circuitry output signal; and combine the second crosstalk cancellation signal with a signal indicative of the first audio signal to generate a second crosstalk cancellation circuitry output signal; and output stage circuitry configured to: receive the first crosstalk cancellation circuitry output signal and, based on the received first crosstalk cancellation circuitry, generate a first drive signal for driving a first speaker to generate the first acoustic signal
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Dayong ZHOU, Brad ZWERNEMANN, Kaichow LAU, Dana J. TAIPALE, John L. MELANSON
  • Patent number: 11855184
    Abstract: A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 26, 2023
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Soo Chang Kang, Seong Jo Hong
  • Publication number: 20230412976
    Abstract: The application describes a switched driver (401) for outputting a drive signal at an output node (402) to drive a load such as a transducer. The driver receives respective high-side and low-side voltages (VinH, VinL) defining an input voltage at first and second input nodes and has connections for first and second capacitors (403H, 403L). A network of switching paths is configured such that each of the first and second capacitors can be selectively charged to the input voltage, the first input node can be selectively coupled to a first node (N1) by a path that include or bypass the first capacitor, and the second input node can be selectively coupled to a second node (N2) by a path that includes or bypasses the second capacitor. The output node (402) can be switched between two switching voltages at the first or second nodes. The driver is selectively operable in different operating modes, where the switching voltages are different in each of said modes.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Anthony S. DOY, Eric J. KING
  • Publication number: 20230409348
    Abstract: In an example there is provided an integrated circuit configured to perform a plurality of functions, the integrated circuit comprising a memory, wherein each function of the integrated circuit is configured to transmit a request to a processor, and wherein the integrated circuit is configured such that the first function to detect that its request has been serviced by the processor is configured to download firmware and/or configuration data for itself and for at least one other function.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 21, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: David HISKY, Daniel WEBER, Jonathan E. EKLUND, Adam BRICKMAN
  • Publication number: 20230408596
    Abstract: Circuitry for determining an impedance of an electrochemical cell comprising at least one first electrode and a second electrode, the circuitry comprising: drive circuitry configured to apply a stimulus to the electrochemical cell; sense circuitry configured to measure a response of the electrochemical cell to the stimulus; and processing circuitry configured to: determine an estimated transfer function of the electrochemical cell based on the stimulus and the response; determine a score for the estimated transfer function; and adjust the stimulus or circuitry used to measure the response based on the score.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 21, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: John P. LESSO, Yanto SURYONO, Toru IDO
  • Publication number: 20230408597
    Abstract: Circuitry for a resistance of an electrochemical cell comprising at least one first electrode and a second electrode, the circuitry comprising: drive circuitry configured to apply a stimulus to the at least one first electrode of the electrochemical cell; sense circuitry configured to measure a response of the electrochemical cell to the stimulus, the response comprising a faradaic component and a non-faradaic component; and processing circuitry configured to: sample the response at a sample time, the sample time selected to maximise a ratio of the non-faradaic component to the faradaic component; and determine the resistance of the electrochemical cell based on the response at the sample time.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 21, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventor: John P. LESSO
  • Patent number: 11843043
    Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: December 12, 2023
    Assignee: Tower Semiconductor Ltd.
    Inventors: Ruth Shima-Edelstein, Ronen Shaul, Roy Strul, Anatoly Sergienko, Liz Poliak, Ido Gilad, Alex Sirkis, Yakov Roizin
  • Publication number: 20230396167
    Abstract: Control circuitry for controlling a current through an inductor of a power converter, the control circuitry comprising: comparison circuitry configured to compare a measurement signal, indicative of a current through the inductor during a charging phase of the power converter, to a signal indicative of a target average current through the inductor for the charging phase and to output a comparison signal based on said comparison; detection circuitry configured to detect, based on the comparison signal, a crossing time indicative of a time at which the current through the inductor during the charging phase is equal to the target average current for the charging phase; and current control circuitry configured to control a current through the inductor during a subsequent charging phase based on the crossing time.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventor: Malcolm BLYTH
  • Publication number: 20230384390
    Abstract: Circuitry for determining an impedance of an electrochemical cell comprising at least one first electrode and a second electrode, the circuitry comprising: drive circuitry configured to apply a stimulus to the electrochemical cell, the stimulus having a stimulation frequency and a stimulation amplitude; and measurement circuitry configured to: measure an output of the electrochemical cell to generate an output signal; separate the output signal into a linear component and a non-linear component; and determine the impedance of the cell based on the linear component of the response.
    Type: Application
    Filed: April 26, 2023
    Publication date: November 30, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventor: John P. LESSO