Abstract: The topology and the shape of sensing electrodes (4, 31) on the Capacity Touch Pad Sensor that allow sensing of small targets are disclosed. Sensor construction utilizes common PCB manufacture technique.

Abstract: Methods and apparatuses are provided for monitoring an inductor output current delivered to a load by a power converter. For example, there is provided an apparatus comprising: at least one power switch operatively coupled to an input voltage source; an output inductor operatively coupled to the at least one power switch and to the load; and a current sensor operatively coupled to the output inductor, the current sensor providing a current sense signal corresponding to the inductor output current delivered to the load. In one embodiment, the current sensor comprises: a filter comprising a first resistor coupled in series with a first capacitor; and a second capacitor coupled in parallel with the first resistor, the first and second capacitors forming an AC voltage divider to increase the signal-to-noise ratio of the current sense signal.

Abstract: In a switched mode power supply (SMPS) that regulates an output voltage in response to load conditions by switching an inductor circuit between a supply voltage and ground at a switching frequency, under light loading conditions, the switching frequency of the SMPS is reduced down to a variable minimum switching frequency sufficiently high to avoid audible noise generation.

Abstract: In a switched mode power supply (SMPS) then selectively operates in continuous current mode (CCM) and discontinuous current mode (DCM), the minimum switching frequency of the SMPS is adjusted by setting a minimum duration for DCM operation. A resistance value applied to an external pin of the SMPS controls the duration of a timer that is reset in CCM and activated upon entering DCM. Upon expiration of the variable duration, the SMPS reverts to CCM for at least one switching cycle. This allows the SMPS minimum effective switching frequency to be set, for each application in which the SMPS is deployed, at a level that avoids audible noise (but which may be lower than an ultrasonic frequency), thus taking maximum advantage of the efficiencies of DCM operation under light load conditions.

Abstract: A plurality of LEDs is driven in parallel, in at least two modes. In a first mode, the LEDs are driven with a first voltage. In subsequent modes, the LEDs are driven with successively higher voltages. The forward voltage drop for each LED is monitored, and the driver switches from the first mode to successive modes based on the largest of the LED forward voltage drops. The current through each LED is controlled by directing a reference current through a first digitally controlled variable resistance circuit, and directing the LED current through a second digitally controlled variable resistance circuit having substantially a known ratio to the first variable resistance circuit and connected in series with the LED. A digital count is altered based on a comparison of the first and second currents, and the first and second variable resistance circuits are simultaneously altered based on the digital count.

Abstract: A voltage regulator improves its transient adjustment response by amplifying error in its regulation feedback control path, including any droop-related error. Amplifying the error speeds up the voltage regulator's response to load changes and droop control adjustments by exaggerating the feedback error. Thus, in at least one embodiment, a droop control circuit imparts a droop-related offset between an output feedback signal and a reference signal responsive to a droop adjustment signal, and a response-enhancing amplifier circuit amplifies that offset for input to an error sensing circuit of a regulation control circuit. The gain and frequency response of the response-enhancing amplifier circuit may be set as a function one or more regulation stability criteria, and the response-enhancing method may be adapted to a variety of voltage regulator topologies. Such topologies include, but are not limited to, PWM regulators and hysteretic regulators.

Abstract: A power system comprising a front end regulator coupled to an input supply voltage (Vin) and providing a regulated input supply voltage (Vbp). The front end regulator compares the input supply voltage (Vin) and the regulated input supply voltage (Vbp) and maintains a substantially constant voltage difference between the input supply voltage (Vin) and the regulated input supply voltage (Vbp) to thereby reduce ripple of the input supply voltage (Vin). A DC-DC switching mode power converter is operatively coupled to the front end regulator and receives the regulated input supply voltage (Vbp). The DC-DC switching mode power converter thereby provides a regulated output voltage (Vout).

Abstract: In a switched mode power supply (SMPS) then selectively operates in continuous current mode (CCM) and discontinuous current mode (DCM), the minimum switching frequency of the SMPS is adjusted by setting a minimum duration for DCM operation. A resistance value applied to an external pin of the SMPS controls the duration of a timer that is reset in CCM and activated upon entering DCM. Upon expiration of the variable duration, the SMPS reverts to CCM for at least one switching cycle. This allows the SMPS minimum effective switching frequency to be set, for each application in which the SMPS is deployed, at a level that avoids audible noise (but which may be lower than an ultrasonic frequency), thus taking maximum advantage of the efficiencies of DCM operation under light load conditions.

Abstract: An apparatus and method for measuring output current and power in real-time is provided for a CPU core powered by a DC-to-DC power converter having active voltage positioning. In an embodiment of the invention, a switched mode power converter comprises at least one power switch operatively coupled to an input voltage source, an output filter operatively coupled to the at least one power switch to provide an output voltage and output current to a load, and a control circuit coupled to the at least one power switch. The control circuit activates the power switch with a duty cycle controlled to regulate at least one of the output voltage and the output current. The control circuit receives a first control signal defining a desired value for the output voltage, a second control signal defining a relationship between voltage input and current draw for the load, and a voltage sense signal corresponding to an actual value of the output voltage. The control circuit thereby provides a measurement of load current.

Abstract: A power supply for plural loads coupled in parallel comprises a voltage regulator, a plurality of current regulators, and an error control circuit. The voltage regulator provides a common output voltage to the plural loads. The voltage regulator comprises a sensor circuit providing a voltage sense signal corresponding to the output voltage, which provides feedback to regulate the output voltage at a selected level. The plurality of current regulators are coupled to respective ones of the plural loads. Each of the plurality of current regulators regulates current drawn by respective ones of the plural loads to within a desired regulation range. The plurality of current regulators each further provide a respective error signal corresponding to an ability to remain within the desired regulation range. The error control circuit is operatively coupled to the voltage regulator and to the plurality of current regulators.

Abstract: A system and method of reducing the pulse width differential in a phase frequency detector (PFD) is provided. In a first embodiment, a PFD is construed using a plurality of flip-flops (or clocking devices) and a plurality of logic gates. A first set of flip-flops are adapted to receive a plurality of inputs and a plurality of clocks and to latch the inputs at transitions in the clocks. A first logic gate is then used to reset the first set of flip-flops and a second set of flip-flops if the inputs are latched (i.e., the clocks are active). If an input is not latched (i.e., a clock is inactive), then the first and second set of flip-flops are not reset, and the outputs of the PFD are forced to zero. Once the inactive clock is reactivated, a third set of flip-flops is used to hold the first set of flip-flops in a reset state for a period of time (e.g., half a clock cycle). Once the period of time elapses, the first set of flip-flops is released from its reset state, and normal operation is resumed.

Abstract: A precision measurement unit (PMU) includes a force amplifier selectively providing either a forcing voltage or a forcing current to a device under test via an output force terminal. A low limit voltage clamp and a high limit voltage clamp are operatively coupled to the output force terminal. The low and high limit voltage clamps are each responsive to user programming to define respective low and high voltage limits at the output force terminal. Upon detection of a reversal of said user programming, the operation of the low and high limit voltage clamps is disabled. More particularly, a comparator is adapted to compare the low and high voltage limits and provide a corresponding disabling signal if the high voltage limit is lower than the low voltage limit.

Abstract: A switched mode power converter includes a transformer having a primary winding, a secondary winding, and a bias winding. A primary side power switch is coupled to the primary winding and is adapted to periodically apply an input voltage to the primary winding. An output filter is operatively coupled to the secondary winding to provide an output voltage and output current. A forward synchronous rectification device is operatively coupled in series between the secondary winding and the output filter. A free-wheeling synchronous rectification device is operatively coupled in shunt with the secondary winding and the output filter. A control circuit is coupled to the bias winding and the forward and free-wheeling synchronous rectification devices.

Abstract: A control circuit for a switched mode power converter is adapted to receive a current sense signal reflecting the output current of the power converter and a feedback signal reflecting the output voltage of the power converter. The control circuit includes a first over-current protection circuit adapted to shut off operation of the switched mode power converter if a sum of the current sense signal and the feedback signal exceed a first predetermined limit, and a second over-current protection circuit adapted to regulate operation of said primary side power switch responsive a comparison of the sum of the current sense signal and the feedback signal to a second predetermined limit. The second predetermined limit is less than the first predetermined limit.

Abstract: An adaptive output driver circuit utilizes an initial point matched impedance model to match the impedance of an output driver to the transmission line and produce an initial step voltage into the transmission line that is half of the desired final voltage. The driver output impedance is controlled by comparing a model of the actual working output stage to a target resistance given by the user. Control signals used to calibrate the impedance of the model to match the target are also used to adjust the working output buffer, so that when the impedance of the model matches the target, the impedance of the working buffer also matches the target impedance.

Abstract: Hermetically sealed high-voltage assemblies are made up of series-connected diodes. Exposed tabs bonding adjacent diodes allow for greater thermal dissipation than previous products. This allows higher current-carrying capacity especially if used in oil.

Abstract: A phase detector and signal locking system controller for use in a digital phase-locked loop (PLL) application includes a first and a second phase detector where the first phase detector result is used to control the initial pull-in and the second phase detector is used to control fine tuning once the phase differences are too small for appropriate detection by the first phase detector. A post processing and control unit operates to effectively merge the two phase detector outputs and to apply the appropriate gain factor that can be used to control a PLL system.

Abstract: A pipelined processor such as an averaging filter including at least one subtractor section and at least one adder section. Both of the subtractor section and the adder section have a plurality of adder logic units. In comparison to the conventional processor, the processor of the present invention is streamlined by the application of one or more of three techniques. First, there is the interleaving approach where the subtractor section and the adder section are interleaved with one another. Second, there is the one delay feedback approach where the adder section includes a one delay feedback for each of the adder logic units. Third, there is the delay enable signal output approach where the averaging filter includes a delay enable signal output for each of the adder logic units of the adder section.

Abstract: Improved digital to analog converter (DAC) circuitry incorporating the ability to utilize a single DAC to generate either voltage or current outputs, and the ability to digitally adjust the gain and offset. Previous digital to analog circuitry has been limited to a single type of analog output per DAC and to the use of external precision resistors to set the gain and offset for a single DAC, or a group of DACs. By utilizing the same on-chip circuitry to supply both types of outputs, chip area, power consumption and cost is reduced while offering more flexibility to the customer. The ability to digitally adjust the gain and offset for a group of DACs eliminates the cost of external resistors, lowers the board area, and lowers the assembly cost for the end product. In addition, since gain and offset can be adjusted dynamically, maximum flexibility is provided to the customer.

Abstract: A clock synthesizer produces an output clock that has a programmable phase offset from the input clock. The clock synthesizer includes an accumulator and an offset adder. The output clock is derived from the offset adder. The offset adder receives a value derived from the accumulator and a selected phase offset value. The phase difference between the non-aligned output clock and the aligned output clock is determined by the phase offset value. The time resolution of the clock synthesizer may be defined by the clock rate of the system and the number of bits used in the offset adder and the accumulator.