Abstract: According to one aspect of the teachings herein, a DC-to-DC converter operates according to an advantageous constant on-time topology that reduces output voltage ripple during light load conditions. The converter produces an output voltage by driving high-side and low-side switches in an inductor-based switching circuit, and regulates the output voltage by varying the on-time of a low-side switch, while holding the on-time of the high-side switch constant. Advantageously, the converter shortens the on-time of the high-side switch during light load conditions, which reduces the output voltage ripple. Thus, the converter may be understood as using a first, constant on-time for the high-side switch during “normal” operations and a second, shorter on-time for the high-side switch during light load conditions.

Abstract: A differential resistor-based digital-to-analog converter (RDAC) can include a positive digital-to-analog converter (PDAC) stage and a negative digital-to-analog converter (NDAC) stage. A first network of resistors of the PDAC stage can be electrically coupled to a second network of resistors of the NDAC stage utilizing an intermediary network of resistors. Further, a differential receiver can include a first input and a second input. The first input can be electrically coupled to a first resistor of the intermediary network of resistors, and the second input can be electrically coupled to a second resistor of the intermediary network of resistors. Furthermore, a portion of the first network of resistors can be electrically coupled to a positive output of the RDAC, and another portion of the second network of resistors can be electrically coupled to a negative output of the RDAC.

Abstract: A differential resistor-based digital-to-analog converter (RDAC) can include a positive digital-to-analog converter (PDAC) stage and a negative digital-to-analog converter (NDAC) stage. A first network of resistors of the PDAC stage can be electrically coupled to a second network of resistors of the NDAC stage utilizing an intermediary network of resistors. Further, a differential receiver can include a first input and a second input. The first input can be electrically coupled to a first resistor of the intermediary network of resistors, and the second input can be electrically coupled to a second resistor of the intermediary network of resistors. Furthermore, a portion of the first network of resistors can be electrically coupled to a positive output of the RDAC, and another portion of the second network of resistors can be electrically coupled to a negative output of the RDAC.

Abstract: A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die.

Abstract: A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell.

Abstract: The final cell or cells in a cascade or ladder of voltage elevator cells may be exposed to significant overvoltages from electrostatic discharge originating in off-chip loads. In such conditions, the final cell or cells may be damaged or destroyed by such overvoltages. Protective circuitry may be added to one or more of the final voltage elevator cells to reduce or eliminate such damage or destruction by distributing the overvoltage among two or more cells. Such protective circuitry may include a capacitor coupled in parallel with the input and output node of one or more of the final voltage elevator cells. The protective circuitry may also include a resistor coupled in series between the final voltage elevator cell and the load.

Abstract: A capacitive touch sensor and LED driver device achieves a reduction in pin count by multiplexing LED drive functionality and capacitive sense functionality on each input/output pin. A control circuit switches between LED drive mode and capacitive sense mode at a frequency of approximately 200 Hz, although other switching frequencies can be used. A bias driver functions as a current sink for LEDs in LED drive mode and can also be used to drive a bias voltage to the LEDs during capacitive sense mode to improve noise immunity.

Abstract: A method and apparatus of primary side output voltage sensing for a flyback power converter preserves secondary-side tranformer isolation without the use of opto-isolators and does not require multiple high-speed sample and hold circuits. A timing circuit measures the duration of the diode conduction interval during a first PWM control cycle and applies this measurement to set the voltage sampling time of the feedback loop during the next PWM cycle. The voltage sampling time for the next PWM cycle is configurable and may be set to occur near the middle of the diode conduction interval or near the end of the diode conduction interval. The cycle-to-cycle PWM duty cycle adjustment step size may be limited to ensure that the diode conduction interval does not vary substantially from cycle to cycle.

Abstract: Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.

Abstract: Examples of systems and methods are provided for converting an analog input signal to a digital output signal. A system may include a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current. A comparator circuit may be configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal. A successive approximation register circuit may be configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal. The DAC-code signal may be used by the CM DAC circuit to control the DAC current.

Abstract: Examples of circuits and methods are provided for common mode stability and bandwidth broadening. A current generator circuit may include a first and a second transistor. Each of the first and second transistors includes a first, second, and third terminal. The first and second transistors provide a first and a second output current at their corresponding third terminals. A first branch including a first resistor and a first capacitor coupled in series is coupled between the third terminal of the first transistor and the first terminal of the second transistor. A second branch including a second resistor and a second capacitor coupled in series is coupled between the third terminal of the second transistor and the first terminal of the first transistor. The first and the second branches are configured to enable the current generator circuit to provide the first and second currents with improved common mode stability.

Abstract: A system and method of synchronizing clocks in a distributed network is disclosed. A simple 1-pulse-per-second timing pulse is routed to time-stamping units in each network device and utilized to measure traffic-dependent synchronization packet residence delays within network elements. Synchronization messages are updated to reflect the measured residence times, thus creating transparent clocks that can readily be synchronized across the network. The simple timing pulse architecture allows the method to be applied readily both to new designs and to retrofit existing hardware.

Abstract: Described herein is a distributed analog loop filter that can be employed in a phase locked loop or a delay locked loop. A circuit block of the distributed analog loop filter includes at least two parallel equivalent circuit elements. The parallel equivalent circuit elements each have an input line. The input lines for each of the parallel equivalent circuit elements are activated sequentially, one after the other. The parallel equivalent circuit elements have sequentially produced outputs that are also activated sequentially, one after another. The parallel equivalent circuit elements extend the tuning range of distributed analog filter while reducing noise associated with the distributed analog filter.

Abstract: Systems and methods are provided for an optical modulation feedback circuit. The feedback circuit includes a low frequency comparison circuit configured to receive a monitoring signal generated by an optical detector, the monitoring signal being proportional to an amount of light generated by an optical transmission device that transmits based on a data signal that is received by an optical driver. The comparison circuit is further configured to generate a modulation control feedback signal that is transmitted to the optical driver based on a comparison of a low frequency component of the monitoring signal and a low frequency component of the data signal.

Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.

Abstract: Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal.

Abstract: Examples of high-speed ball grid array packages and a process of forming a package are provided. A package may include contact pads disposed on a bottom surface, conductive balls, and a signal via structure. The package may also include a first ground via structure arranged along one or more first semi-circular contours around the signal via structure and extending vertically and a second ground via structure arranged along one or more second semi-circular contours around the signal via structure and extending vertically. The package may include a ground interface plane disposed in separation from the signal contact pad by a distance. The distance may be determined based on at least a size of the signal contact pad, a dielectric constant of a transition layer between the ground interface plane and the signal contact pad, and a distance between the signal via structure and the second ground via structure.

Abstract: Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal.

Abstract: A system and method for controlling a digital pulse-width modulated power converter achieves a fast large-signal transient response while maintaining a slow response near the steady-state operating point in order to assure stability and to reduce the system's susceptibility to noise. Digital output error samples are processed through a gain scheduling block that applies a non-linear gain function to produce a weak loop response when the system is near its steady-state equilibrium point and a strong loop response when large transients are encountered. The resulting system maintains a fast transient response to large error signals while reducing noise and loop jittering and assuring loop stability.

Abstract: A system and method is provided for preventing a dropout of an LED current. In one embodiment of the present invention, the system includes a voltage source, a first circuit, a second circuit, a controller, and at least one LED. The first circuit receives a reference voltage from the voltage source, receives set-point current data from the controller, and uses the reference voltage and the set-point current data to produce a threshold voltage. The threshold voltage is then provided to the second circuit, where it is converted into an output current, which is drawn through the LED. The second circuit then compares the threshold voltage to an output voltage corresponding to the output current, and provides an output to the controller. The controller then uses the output to determine whether a dropout has occurred. If a dropout has occurred, then second set-point current data is provided to the first circuit.