Abstract: Examples are provided for a multi-stage track-and-hold amplifier (THA). The multi-stage THA may include a first stage, a second stage, and a third stage. The first stage may be coupled to an input signal and configured to sample the input signal. The second stage may be coupled to the first stage and may include a buffer circuit. The third stage may be coupled to the second stage and can include a bootstrapped THA. The first stage may further include a shunted source-follower circuit and a switched source-follower circuit. The shunted source-follower circuit may include a first switch that can be operable to couple an output node of the shunted source-follower circuit to ground potential.

Abstract: A mobile device includes a conductive element and a ground node. The conductive element is configured to be detected by a proximity sensor. A switch is coupled between the conductive element and ground node. The conductive element is coupled to the ground node by closing the switch. A first memory element is configured to control the switch. The first memory element includes a register bit coupled to a control terminal of the switch. A data output is configured to control the switch. A FIFO is configured to provide data to the data output. The first memory element includes a FIFO. A capacitive touch controller is configured to measure a capacitance of the conductive element. A digital processing unit is configured to convert the capacitance of the conductive element to a bit of data. A second memory element is configured to store the bit of data.

Abstract: Systems and methods are provided for a low frequency AC comparison circuit. The low frequency AC comparison circuit includes circuitry configured to receive a monitoring signal generated by an optical detector, the monitoring signal being proportional to an amount of light generated by an optical transmission device that transmits based on a data signal that is received by an optical driver. The comparison circuit is further configured to generate a modulation current control signal that is transmitted to the optical driver based on a comparison of a low frequency AC component of the monitoring signal and a correlated low frequency AC component of the data signal.

Abstract: A transmitter device arranged to encode a set of digital input data into a succession of modulated chirps, whereby said digital input data are encoded according to a Gray code into codewords (320, 321, 322) having a plurality of bits, and having an interleaver that distributes the bits (C00, . . . Cnn) of each codeword into a series of digital modulation values (S0, . . . S7), at different bit positions, and to synthesize a series of modulated chirps whose cyclical shifts are determined by the modulation values. A special frame structure is defined in order to ensure high robustness, and variable bit-rate flexibility.

Abstract: Described herein are systems and methods for reducing power consumption, latency, and chip complexity in a datacom/telecom multiplexer and demultiplexer. Adding a high frequency analog domain data path around or in place of a standard digital core data path allows the elimination of the demultiplexing and multiplexing stages required to drop the data rate of data streams down to that required for a standard digital core. Latency is also reduced due to the higher operating frequency of sequential elements required for data operations. The digital core can be powered down when not in use, and can be activated when necessary.

Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

Abstract: Examples are provided for a method and apparatus for calibration of an analog-to-digital converter (ADC) including multiple sub-ADCs. The method includes applying a calibration signal to an input node of each sub-ADC. For each sub-ADC, a corresponding error signal is generated based on output signals of the sub-ADC and a reference sub-ADC. Each sub-ADC is calibrated based on the corresponding error signal. The reference sub-ADC is selected by: applying a non-zero input voltage signal to the input node of each sub-ADC, measuring a corresponding output signal of each sub-ADC in response to the non-zero input voltage signal, generating a deviation error based on a subtraction of a stored value from the measured output signal of each sub-ADC, and designating as the reference sub-ADC a sub-ADC from the multiple sub-ADCs based on the deviation error.

Abstract: A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength.

Abstract: Examples are provided for time-interleaved analog-to-digital conversion with redundancy. The redundancy may include high-order and nested redundancies. An apparatus may include multiple analog-to-digital converter (ADC) blocks coupled to one another to form a time-interleaved ADC. Each ADC block may include multiple ADC slices, wherein a count of the ADC blocks is M and some of the ADC slices may be redundant slices. A clock circuit may be configured to provide multiple clock signals. A portion N of M ADC blocks may be configured to be active, in a normal mode of operation, where N and M are integer numbers and N is smaller than M. A remaining portion of the M ADC blocks may be redundant ADC blocks, one or more of which may be selectively active, in a healing mode of operation, and be swapped for one or more failed ADC blocks using the plurality of clock signals.

Abstract: A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength.

Abstract: An apparatus and method for the use of a resistive touch screen as a proximity sensor. The touch screen operates in a touch sensing mode and a proximity sensing mode. The proximity sensing mode turns off the touch sensing circuit and uses the equivalent capacitor formed by the top layer of the touch screen with a nearby object to detect proximity. A control circuit selectively connects the touch screen with measurement circuits to perform each of the sensing functions. The control circuit can be implemented with timing based control or an event driven topology.

Abstract: Described herein are systems and methods that facilitate the measurement of the capacitance of high voltage devices while shielding an active device involved in the measurement from the high voltage. The systems and methods employ capacitors to store the high voltage such that the active device does not experience the high voltage. Placement of a reset device ensures that the active device is shielded from the high voltage.

Abstract: Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively.

Abstract: A high speed transmit driver is provided, along with methods to improve driver slew rate, decrease transmit jitter, improve termination accuracy, and decrease sensitivity to supply noise.

Abstract: Examples are provided for a time-interleaved analog-to-digital converter (ADC) with built-in self-healing. The ADC may include multiple ADC slices. Each ADC slice may be configured to operate in one of a normal or a healing mode of operation. In the normal mode of operation, each ADC slice may convert an input analog signal to a single digital output signal in response to a clock signal associated with the ADC slice. In the healing mode of operation, each ADC slice may be operable to convert the input analog signal to two or more digital output signals in response to two or more clock signals. One or more of the digital output signals may replace one or more output signals of failed ADC slices. A first clock signal may be associated with the ADC slice. A second clock signal may be associated with another ADC slice of the plurality of ADC slices.

Abstract: Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage.

Abstract: A semiconductor device measures a state of a MEMS as a first voltage variation at a sensing node. The state of the MEMS includes a capacitance. A first capacitor is coupled between the sensing node and an input of an integrator for transferring the first voltage variation to a second node as a first signal. A second voltage variation is routed through a second capacitor to the second node as a second signal. The integrator integrates the first signal and second signal to provide an integrated signal. An ADC has an input coupled to an output of the integrator and converts the integrated signal to a digital signal representative of the capacitance of the MEMS. A DAC has an input coupled to the output of the ADC. A second capacitor is coupled between an output of the DAC and the sensing node.

Abstract: A pipeline analog-to-digital converter is disclosed. An example of a pipeline analog-to-digital converter comprises a plurality of stages. Each of the plurality of stages comprises an analog-to-digital conversion circuit comprising a comparator configured to produce an n-bit digital domain output; and a switchable conductance digital-to-analog conversion circuit operatively coupled to the comparator and configured to switch between at least two conductance values in response to a value of the n-bit digital domain output.

Abstract: A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input.

Abstract: Described herein are systems and methods for providing a variable switching frequency for a power supply. The system includes a controller and a filter. The controller generates a switching frequency for a power supply. The switching frequency is modified as a function of an input voltage and an output voltage. The filter provides the output voltage to a load based at least in part on the switching frequency generated by the controller. In one example, the controller adaptively modifies the switching frequency as a function of the input voltage and the output voltage in order to maintain a peak to peak current for an inductor.