Abstract: A pre-amplifier located "at the focal plane" of a detector array is disclosed which uses MOSFET transistors operated in the "weak inversion" region to provide operational amplifier performance. The dimensions of certain of the transistors are designed to minimize noise amplification. Feedback resistance for the operational amplifier is provided by switched capacitance using MOSFET transistors as switches, thereby permitting adjustment of the amplifier gain. Implanted and non-implanted MOSFET transistors are used in the differential amplifier in such a way as to avoid the need for a biasing network.

Abstract: A photo detector array module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of photo-detectors on the focal plane end, and of thin film circuitry on the back plane end, each plane is etched to cut back the semiconductor material, then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Abstract: A high-density electronic package module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of thin film circuitry on the access ends, each access plane is etched to cut back the semiconductor material then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Abstract: A multiplexer circuit is disclosed, for use with such signal sources as focal plane detector arrays, which contains a large number of parallel branches, each of which includes a transconductance MOSFET amplifier and a MOSFET switch of opposite channel polarity from the amplifier. The amplifier in each branch receives high impedance voltage signals originating from its individual detector and converts them with high power gain into current signals which feed into the common output line whenever the switch in the same branch is turned on. The multiplexer branches, together with the multiplexer control logic, and other electronic devices, are all included on a signal IC chip which provides CMOS logic.

Abstract: A focal plane photo-detector mosaic array is disclosed in which thin stacked substrate layers extending in planes perpendicular to the focal plane provide closely spaced electrical contact points at the focal plane, and photo-detectors on the focal plane which individually communicate with those contact points are arranged in rows extending diagonally with respect to the planes in which the stacked substrate layers extend.

Abstract: A photo-detector array module is disclosed wherein: (a) the focal plane array of photo-detectors is in electrical contact with thin film conductors supported on thin ceramic layers extending perpendicular to the focal plane, and (b) sub-module structures, each composed of such layers, have complementary shapes (such as "O-shaped" and "I-shaped") to provide "component wells" for electronics within the three dimensional space defined at one end by the two-dimensional area of the focal plane. In order to fabricate such a module satisfactorily, a method is disclosed in which each unimaged layer (i.e., layer whereon the thin film conductors have not yet been photodelineated) is individually laminated to the prior structure, and the photo-delineation process on the unimaged layer includes an optical alignment step to insure alignment of the thin film conductors on each layer with those on preceding layers.

Abstract: A photo-detector array module is disclosed wherein: (a) the focal plane array of photo-detectors is in electrical contact with thin film conductors supported on thin ceramic layers extending perpendicular to the focal plane, and (b) sub-module structures, each composed of such layers, have complementary shapes (such as "O-shaped" and "I-shaped") to provide "component wells" for electronics within the three dimensional space defined at one end by the two-dimensional area of the focal plane. In order to fabricate such a module satisfactorily, a method is disclosed in which each unimaged layer (i.e., layer whereon the thin film conductors have not yet been photo-delineated) is individually laminated to the prior structure, and the photo-delineation process on the unimaged layer includes an optical alignment step to insure alignment of the thin film conductors on each layer with those on preceding layers.

Abstract: A photo-detector array module is disclosed wherein: (a) the focal plane array of photo-detectors is in electrical contact with thin film conductors supported on thin ceramic layers extending perpendicular to the focal plane, and (b) sub-module structures, each composed of such layers, have complementary shapes (such as O-shaped and "I-shaped") to provide "component wells" for electronics within the three dimensional space defined at one end by the two-dimensional area of the focal plane. In order to fabricate such a module satisfactorily, a method is disclosed in which each unimaged layer (i.e., layer whereon the thin film conductors have not yet been photo-delineated) is individually laminated to the prior structure, and the photo-delineation process on the unimaged layer includes an optical alignment step to insure alignment of the thin film conductors on each layer with those on preceding layers.

Abstract: The apparatus comprises a parallel coil and a capacitance, the coil having an air gap in which an unknown specimen is inserted, a source of alternating voltage applied to the coil-capacitance combination, scanning means for automatically varying the value of the capacitance in steps, thus varying the phase of the voltage across the coil, means for digitizing the phase of the voltage corresponding to each capacitance value, a memory in which those digitized phase values are stored, a reference memory containing digitized phase values for known specimens, and means for comparing the digitized phase values of the unknown specimen with those of known specimens. A digital tolerance control circuit is also provided which accommodates deviations between the reference and the known phase values, up to predetermined amounts, and means are provided for displaying the generic name or grade of the stored phase values which match the phase values of the unknown specimen.

Abstract: A digital eddy current apparatus for sensing and analyzing metallurgical characteristics of an electrically conductive material. A square wave is supplied to a resonating circuit which includes a coil used as a sensing element for the conductive material. The resonating circuit produces a sinusoidal wave which is converted into a rectangular pulse which, when the resonating means is at resonance condition if superimposed upon the square wave pulse it would be positioned in the center of one-half of the square wave. The width of the rectangular pulse is a direct function of the amplitude of the sinusoidal wave and phase shift of the sinusoidal waveform is detected by movement of the rectangular pulse from the center position within the square wave. The width and position of the rectangular pulse is a direct function of the metallurgical characteristics of the conductive material.