Patents Assigned to Sensor Corporation
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Patent number: 6867806Abstract: In a CMOS-type image sensor, a plurality of pairs of light-detecting elements (LDEs) are arranged in rows and columns to generate analog signals proportional to the intensity of light impinging on respective one of the LDEs. First and second photo sensing means in each pair of LDEs are coupled in parallel, in the column direction, at a floating sensing point through first turn-on means. The first and second photo sensing means in adjacent pairs of LDEs are coupled in parallel in the column direction through second turn-on means. The first turn-on means are enabled by first control lines and the second turn-on means are enabled by second control lines coupled thereto, respectively. Analog signals acquired in the first and second photo sensing means of one pair or of adjacent pairs are present at the floating sensing point in response to the enabling of the first or second control lines, respectively.Type: GrantFiled: November 4, 1999Date of Patent: March 15, 2005Assignee: Taiwan Advanced Sensors CorporationInventors: Sywe N. Lee, David Wayne
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Patent number: 6856167Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as mXN where m is the number of word width bits per memory chip and N is the number of memory chips.Type: GrantFiled: January 17, 2003Date of Patent: February 15, 2005Assignee: Irvine Sensors CorporationInventors: Volkan H. Ozguz, Randolph S. Carlson, Keith D. Gann, John P. Leon
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Patent number: 6829237Abstract: A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a second plurality of output ports (190) comprising: a first stack (140) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (142); a second stack (160) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer (113) containing at least one switching element circuit (162); and interconnecting circuitry (150) that connects the first stack (140) of IC layers to the second stack (160) of IC layers to form the compact multi-stage switching network. The stacks (140, 160) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection.Type: GrantFiled: October 9, 2001Date of Patent: December 7, 2004Assignee: Irvine Sensors CorporationInventors: John C. Carson, Volkan H. Ozguz
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Patent number: 6806559Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metallizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metallizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metallizations, which are disposed in part on the bare insulative surface.Type: GrantFiled: April 22, 2002Date of Patent: October 19, 2004Assignee: Irvine Sensors CorporationInventors: Keith D. Gann, Douglas M. Albert
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Patent number: 6797537Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.Type: GrantFiled: October 30, 2001Date of Patent: September 28, 2004Assignee: Irvine Sensors CorporationInventors: Angel Antonio Pepe, James Satsuo Yamaguchi
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Patent number: 6784547Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.Type: GrantFiled: November 21, 2002Date of Patent: August 31, 2004Assignee: Irvine Sensors CorporationInventors: Angel Antonio Pepe, James Satsuo Yamaguchi
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Patent number: 6753912Abstract: A self-compensating correlated double sampling circuit for a pixel image signal and a method to process the same. In the circuit, the analog signal generated by the photosensor of the pixel array accessed by a row selection transistor is buffered through a source follower amplifier and coupled to a column in the array. The analog signal from the selected column line is fed through a CDS circuit which is then input to the sample and hold circuit of the ADC. The main purpose of the CDS circuit is to reduce the noise and non-uniformity caused by the non ideal effects associated with the signal path from the photosensor through the CDS circuit. This is accomplished by sampling the signal and a reference level and then performing the subtraction on the two samples and the ADC ramp through the same signal path.Type: GrantFiled: August 31, 1999Date of Patent: June 22, 2004Assignee: Taiwan Advanced Sensors CorporationInventor: David A. Wayne
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Patent number: 6734370Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.Type: GrantFiled: September 7, 2001Date of Patent: May 11, 2004Assignee: Irvine Sensors CorporationInventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
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Patent number: 6717061Abstract: Each multilayer module of a plurality of multilayer modules has a plurality of layers wherein each layer has a substrate therein. The plurality of multilayer modules includes a first multilayer module including a first layer and a second multilayer module including a second layer each having a top side and bottom side. The first layer and second layer each includes a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The plurality of multilayer modules further includes a heat-separating layer disposed between the top side of the first layer and the bottom side of the second layer. The first multilayer module is adhered to the second multilayer module and the first multilayer module can be detached from the second multilayer module by applying heat to the heat-separating layer.Type: GrantFiled: September 7, 2001Date of Patent: April 6, 2004Assignee: Irvine Sensors CorporationInventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
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Patent number: 6706971Abstract: A stackable microcircuit layer formed from a plastic encapsulated microcircuit (PEM) and method of making the same is disclosed. The method involves the steps of starting with a commercially available PEM (e.g. a plastic Thin Small Outline Package or TSOP) that contains a microcircuit or die within an encapsulant and modifying the PEM to expose conductive members that are electrically connected to the microcircuit's bond pads. In the case of a TSOP, the preferred modifying step is accomplished by top grinding the TSOP in order to remove the lead frame that was secured above the die and encapsulated along with it in the TSOP. Next, reroute metallization is applied in order to connect the conductive members that were exposed by the top grinding, to an edge of the modified PEM. Finally, if appropriate, the modified PEM is thinned through backside grinding and diced to a desired area, in order to provide a stackable microcircuit layer that may form a part of a dense electronic package.Type: GrantFiled: May 10, 2002Date of Patent: March 16, 2004Assignee: Irvine Sensors CorporationInventors: Douglas M. Albert, Keith D. Gann
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Patent number: 6650704Abstract: A method of processing low resolution input frames containing undersampled views of an optically imaged scene to produce a higher quality, higher resolution output frame. This method operates by obtaining a sequence of low resolution input frames containing different undersampled views of an optically imaged scene.Type: GrantFiled: October 25, 1999Date of Patent: November 18, 2003Assignee: Irvine Sensors CorporationInventors: Randolph S. Carlson, Jack L. Arnold, Valentine G. Feldmus
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Patent number: 6596997Abstract: The illustrated embodiment of the invention is an improvement to an infrared camera in which an uncooled warm stop is provided which includes an array of miniature retro-reflectors on its rear surface oriented toward the detector in the camera and away from the exterior light source of interest instead of having a diffuse (i.e., Lambertian or white) or specular (i.e., mirror-like) reflector on the rear or interior surface of the warm stop.Type: GrantFiled: August 3, 2001Date of Patent: July 22, 2003Assignee: Irvine Sensors CorporationInventor: Charles S. Kaufman
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Patent number: 6560109Abstract: A stack of multilayer modules has a segmentation layer disposed between neighboring multilayer modules. The segmentation layer facilitates the separation of neighboring multilayer modules. The stack of multilayer modules includes a first multilayer module and a second multilayer module. Each multilayer module includes a plurality of active layers each comprising a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The second multilayer module is disposed to be neighboring the first multilayer module with at least one segmentation layer between the first and second multilayer modules. The segmentation layer includes a metal layer and at least one thermoplastic adhesive layer. When heat is applied, the metal layer conducts heat to the thermoplastic adhesive layer.Type: GrantFiled: September 7, 2001Date of Patent: May 6, 2003Assignee: Irvine Sensors CorporationInventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
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Patent number: 6476392Abstract: A temperature dependent focal plane array operates without a temperature stabilization cooler and/or heater over a wide range of ambient temperatures. Gain, offset and/or bias correction tables are provided in a flash memory in memory pages indexed by the measured temperature of the focal plane array. The memory stores a calibration database, which is accessed using a logic circuit which generates a memory page address from a digitized temperature measurement of the focal plane array. The calibration database is comprised of an array of bias, gain and offset values for each pixel in the focal plane array for each potential operating temperature over the entire range of potential operating temperatures. The bias, gain and offset data within the database are read out, converted to analog form, and used by analog circuits to correct the focal plane array response.Type: GrantFiled: May 11, 2001Date of Patent: November 5, 2002Assignee: Irvine Sensors CorporationInventors: Charles S. Kaufman, Randolph S. Carson, William B. Hornback
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Patent number: 6389404Abstract: A neural processing module is disclosed which combines a weighted synapse array that performs “primitive arithmetic” (products and sums) in parallel with a weight change architecture and a data input architecture that collectively maximize the use of the weighted synapse array by providing it with signal permutations as frequently as possible. The neural processing module is used independently, or in combination with other modules in a planar or stacked arrangement.Type: GrantFiled: December 30, 1998Date of Patent: May 14, 2002Assignee: Irvine Sensors CorporationInventors: John C. Carson, Christ H. Saunders
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Patent number: 6117704Abstract: A method and structure are disclosed which involve the re-wafering of previously processed and tested IC chips. The chips are encapsulated in supporting non-conductive material in a neo-wafer, so that they may be further processed preparatory to dicing layer units from the neo-wafer, which layer units are ready for stacking in a three-dimensional electronic package. Although the layer areas are the same, different stacked layers may contain different sized IC chips, and a single layer may encapsulate a plurality of chips. Precision of location of the separate IC chips in the neo-wafer is insured by use of photo-patterning means to locate openings in the neo-wafer into which extend conductive bumps on the chips. The neo-wafer is preferably formed with separate cavities in which the chips are located before they are covered with the encapsulating material.Type: GrantFiled: March 31, 1999Date of Patent: September 12, 2000Assignee: Irvine Sensors CorporationInventors: James S. Yamaguchi, Volkan H. Ozguz, Andrew N. Camien
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Patent number: 6072234Abstract: Neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating ) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually "known good" die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. The following benefits are obtained: (1) The starting IC chips (die) intended for stacking may have different sizes, and serve different electronic purposes. After they are encapsulated in same-size neo-chips, they can be efficiently stacked using well-developed processing steps; (2) The individual chips for stacking can be purchased as "known good" die.Type: GrantFiled: May 21, 1999Date of Patent: June 6, 2000Assignee: Irvine Sensors CorporationInventors: Andrew N. Camien, James S. Yamaguchi
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Patent number: 6028352Abstract: A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is formed by mechanically and electrically joining an IC-containing TSOP with an external leadframe. Each leadframe contains conductors which are disposed to connect with TSOP leads, transpose signals to other locations on the periphery of the TSOP, and/or connect with other layers in the stack. The TSOP/leadframe layers are stacked and joined, and the leadframe terminals of the lowest layer are disposed to facilitate connection with a PCB or other circuitry.Type: GrantFiled: June 10, 1998Date of Patent: February 22, 2000Assignee: Irvine Sensors CorporationInventor: Floyd K. Eide
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Patent number: 6014316Abstract: A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is fabricated by forming one or more flexible circuit around a TSOP. Each flexible circuit contains conductors which are disposed to connect with TSOP leads, transpose signals to or from various locations on the top or bottom of the TSOP, and/or terminate in ball grid contacts for connection to other layers in the stack. The flexible circuit is bonded to the TSOP such that ball grid contacts are exposed on the top and bottom of the TSOP, and the ball grid array contacts on the bottom of the lowest layer are disposed to facilitate connection with a PCB or other circuitry.Type: GrantFiled: June 10, 1998Date of Patent: January 11, 2000Assignee: Irvine Sensors CorporationInventor: Floyd K. Eide
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Patent number: 5955668Abstract: A micro-gyro device is disclosed combining an element which oscillates around the drive axis and an element which rocks around the output axis, so arranged that Coriolis force is transmitted from one element of the other without any substantial transfer of motion of either element to the other in its own direction of motion. In other words, the masses of the two elements operate independently of one another, providing improved performance, and individual adjustability to compensate for any manufacturing imprecision. The presently-preferred device combines an outer ring which oscillates around the drive axis with an inner disk which rocks around the output axis, whenever external rotating motion occurs about the rate axis.Type: GrantFiled: October 5, 1998Date of Patent: September 21, 1999Assignee: Irvine Sensors CorporationInventors: Ying W. Hsu, John W. Reeds, III, Christ H. Saunders