Patents Assigned to SENSOR
  • METHOD FOR ACCURATELY MEASURING REAL-TIME DEW-POINT VALUE AND TOTAL MOISTURE CONTENT OF A MATERIAL
    Publication number: 20160245765
    Abstract: A system and method for accurately measuring the real-time valid dew-point value of a material and determining the total moisture content of the material within the valid dew-point value by using an algorithm during the material drying process. The algorithm estimates the valid dew-point value of the material and the total moisture content of the material by analyzing the sensor data received on a server. The algorithm determines a valid dew-point value by estimating an inflection point for the material, and the total moisture content of the material is determined within the valid dew-point value.
    Type: Application
    Filed: February 21, 2016
    Publication date: August 25, 2016
    Applicant: Prophecy Sensors, LLC
    Inventor: Biplab Pal
  • Heterostructure including anodic aluminum oxide layer
    Patent number: 9425353
    Abstract: A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can be located between a semiconductor layer and another layer of material. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor layer. The layer of material can penetrate at least some of the plurality of pores and directly contact the semiconductor layer. In an illustrative embodiment, the layer of material is a conductive material and the anodic aluminum oxide is located at a p-type contact.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: August 23, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska
  • Sky polarization and sun sensor system and method
    Patent number: 9423484
    Abstract: A system for determining a new orientation and/or position of an object comprises a sky polarimeter configured to record image data of the sky, a signal processing unit, and logic configured to receive and store in memory the image data received from the sky polarimeter. The logic calculates the Stokes parameters (S0, S1, S2,), DoLP, and AoP from the image data, detects obscurants and filters the obscurants (such as clouds and trees) from the image data to produce a filtered image. The logic is further configured to find the Sun and zenith in the filtered image, and to determine the roll, pitch, yaw, latitude and longitude of the object using the filtered image.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 23, 2016
    Assignee: Polaris Sensor Technologies, Inc.
    Inventors: Todd Michael Aycock, David Chenault, Arthur Lompado, J. Larry Pezzaniti
  • Patterned Substrate Design for Layer Growth
    Publication number: 20160240739
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Application
    Filed: April 26, 2016
    Publication date: August 18, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Reflective transparent optical chamber
    Patent number: 9415126
    Abstract: A chamber configured to increase an intensity of target radiation emitted therein is provided. The chamber includes an enclosure at least partially formed by a set of transparent walls. Each transparent wall can comprise a first material transparent to the target radiation and having a refractive index greater than 1.1 for the target radiation. The outer surface of the set of transparent walls can include a set of cavities, each cavity comprising an approximately prismatic void. Additionally, a medium located adjacent to an outer surface of the set of transparent walls can have a refractive index within approximately one percent of a refractive index of a vacuum for the target radiation.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: August 16, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Semiconductor structure with stress-reducing buffer structure
    Patent number: 9412902
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Grant
    Filed: February 22, 2015
    Date of Patent: August 9, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Superlattice structure
    Patent number: 9412901
    Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 9, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Remigijus Gaska, Jinwei Yang, Alexander Dobrinsky
  • Semiconductor Device with Multiple Space-Charge Control Electrodes
    Publication number: 20160225863
    Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.
    Type: Application
    Filed: April 12, 2016
    Publication date: August 4, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Light Emitting Heterostructure with Partially Relaxed Semiconductor Layer
    Publication number: 20160225941
    Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.
    Type: Application
    Filed: April 12, 2016
    Publication date: August 4, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Semiconductor layer including compositional inhomogeneities
    Patent number: 9406840
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 2, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska, Mikhail Gaevski
  • Multi-wafer reactor
    Patent number: 9404182
    Abstract: A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: August 2, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Igor Agafonov, Michael Shur, Alexander Dobrinsky
  • Tool service life sensor with wireless connectivity
    Patent number: 9400765
    Abstract: Apparatus for calculating service life expectancy of wellbore intervention tools comprising one or more sensors, power means, control means and wireless connectivity means. Also a method of the measuring and calculating the service life expectancy of wellbore intervention tools using this apparatus.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 26, 2016
    Assignee: Sensor Development AS
    Inventor: Oivind Godager
  • Stress Relieving Semiconductor Layer
    Publication number: 20160211331
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Patterned layer design for group III nitride layer growth
    Patent number: 9397260
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: July 19, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • IMAGING UNIT OF A CAMERA FOR RECORDING THE SURROUNDINGS WITH OPTICS UNCOUPLED FROM A CIRCUIT BOARD
    Publication number: 20160205300
    Abstract: An imaging unit of a camera for recording the surroundings has an image sensor with a lens for the display of the surroundings on the image sensor. The image sensor and the lens are held by a carrier. The camera additionally has a circuit hoard and at least the signal and the supply lines of the image sensor arranged on the carrier. The image sensor is mounted on a carrier substrate, which similar to the lens, is arranged on the carrier at a distance from the circuit board, and has a flexible electrical connection to the circuit board.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 14, 2016
    Applicant: FIRST SENSOR MOBILITY GMBH
    Inventor: Erik BUSSE
  • Lateral/vertical semiconductor device
    Patent number: 9391189
    Abstract: A lateral semiconductor device and/or design including a space-charge generating layer and a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: July 12, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Mikhail Gaevski, Michael Shur, Remigijus Gaska
  • Lens mounts with locking mechanisms
    Patent number: 9389488
    Abstract: An optical assembly includes a lens mount. The lens mount includes a lens mount body with a threaded lens aperture extending axially therethrough. A ring extends from the lens mount body. The ring defines a lens locking aperture therethrough that is spaced axially apart from the lens aperture and is aligned with the lens aperture. The lens aperture and lens locking aperture are both threaded. A lens element is threaded into the lens aperture and lens locking aperture. A lock operatively connects the lens mount body to the ring for locking the lens element by flexure of the ring relative to the lens aperture.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: July 12, 2016
    Assignee: Sensors Unlimited, Inc.
    Inventor: Laszlo Kovacs
  • Semiconductor Structure with Inhomogeneous Regions
    Publication number: 20160197228
    Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Alexander Lunev, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Deep Ultraviolet Light Emitting Diode
    Publication number: 20160197233
    Abstract: A carbon doped short period superlattice is provided. A heterostructure includes a short period superlattice comprising a plurality of quantum wells alternating with a plurality of barriers. One or more of the quantum wells and/or the barriers includes a carbon doped layer (e.g., a non-percolated or percolated carbon atomic plane).
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Remigijus Gaska, Jinwei Yang, Alexander Dobrinsky
  • Electrode patch array
    Patent number: D764672
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: August 23, 2016
    Assignees: NuLine Sensors, LLC, Techmedic International, BV
    Inventors: Michael J. Vosch, Benjamin M. Downey, Rutger Alexander Brest van Kempen