Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming

Abstract: A MOS transistor capable of withstanding relatively high voltages is of a type integrated on a region included in a substrate of semiconductor material, having conductivity of a first type and comprising a channel region intermediate between a first active region of source and a second active region of drain. Both these source and drain regions have conductivity of a second type and extend from a first surface of the substrate. The transistor also has a gate which includes at least a first polysilicon layer overlying the first surface of at least the channel region, to which it is coupled capacitively through a gate oxide layer. According to the invention, the first polysilicon layer includes a mid-portion which only overlies the channel region and has a first total conductivity of the first type, and a peripheral portion with a second total conductivity differentiated from the first total conductivity. The peripheral portion partly overlies the source and drain active regions toward the channel region.

Abstract: A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

Abstract: A circuit comprises a measurement resistor in series with a heater, a detector circuit for providing a signal indicative of the current flowing in the resistor, switching devices for controlling the connection of the heater to a voltage source and the connection of the measurement resistor in the supply circuit comprising the source and the heater, and a control unit arranged to drive the switching devices in a manner such that each time the heater is activated, the measurement resistor is kept disconnected from the supply circuit of the heater for a predetermined period of time and the measurement resistor is then connected in the supply circuit of the heater.

Abstract: In switch-capacitor systems for extremely low supply voltage, employing a fully differential switched op-amp, proper functioning of nMOS switches coupled to the inverting input node of an integrated stage capable of outputting a common mode control signal is made possible by retaining the ground potential on the input node to prevent body effects on the threshold of nMOS switches by means of an auxiliary switched capacitor.

Abstract: The present invention relates to a method of forming deep trenches in a BICMOS-type integrated circuit wherein the formation of a bipolar transistor includes the steps of depositing a base polysilicon layer, depositing a protection oxide layer, forming an emitter-base opening, and etching the silicon oxide protection layer and the base polysilicon layer outside the bipolar transistor areas. The formation of the trenches includes the steps of opening the protection oxide and base polysilicon layers above a thick oxide region while the emitter-base opening is being made, etching the thick oxide layer while the protection oxide layer is being etched, and etching the silicon under the thick oxide while the base polysilicon is being etched.

Abstract: A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.

Abstract: In a method for the manufacture of cells of a read-only memory, each cell comprises a MOS transistor formed by a first diffusion and a second diffusion of impurities of a first type in a semiconductor substrate with impurities of a second type. These two diffusions are separated by a channel surmounted by a gate. A thick oxide zone is made in the zone designed for the first diffusion, so that the making of the diffusions leads to a first diffusion in two parts separated by this thick oxide zone, a first part adjoining the channel and a second part on the periphery of the transistor. A particular encoding step makes it possible, by means of a mask, to eliminate the thick oxide in certain cells so that these encoded cells have a first continuous diffusion.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract: Disclosed is a load pump type of voltage generator circuit designed to produce several levels of voltage higher than a supply voltage of the circuit. The circuit comprises two cascades of elementary pumping cells. Each cell is controlled by at least one driving signal. To make the two cascades work together, it is planned to modify the driving signal or one of the driving signals assigned to the last cell of the first cascade in such a way that the first cascade delivers a voltage equal to the sum of the voltages delivered by the two cascades. In a particular embodiment, the two cascades comprise the same number of cells and can work in parallel. Application to the field of non-volatile memories for the production of read and write voltages.

Abstract: A failure detector associated with a four-layer semiconductor protection component has a middle layer that corresponds to a low-doped semiconductor substrate of a first conductivity type. The component includes in this substrate, in addition to plurality of regions providing its protection function, at least one additional region of the second conductivity type connected to a test terminal.

Abstract: A semiconductor memory device includes: a plurality of output data terminals; a matrix of memory cells including a plurality of groups of columns of memory cells, each group of columns being associated with a respective output data terminal; column selection means associated with the matrix of memory cells for selectively coupling one column for each of the group of columns to a respective sensing means driving the output data terminal; redundancy columns of redundancy memory cells for functionally replacing defective columns in the matrix; redundancy column selection means associated with the redundancy columns for selectively coupling one redundancy column to a redundancy sensing means; defective address storage means for storing defective addresses of the defective columns and identifying codes suitable for identifying the groups of columns wherein the defective columns are located, for comparing the defective addresses with a current address supplied to the memory device and for driving the redundancy col

Abstract: A voltage regulator for powering a load with a predetermined temperature-stable voltage, including an output stage, a terminal of which provides a current to the load, at a reference voltage; and a current source including a first branch formed of transistors and of a first resistor connected in series between two supply terminals, and a second branch formed of transistors connected in series between the two supply terminals, the output stage including a bipolar transistor connected as a current mirror with a bipolar transistor of the second branch, and the two transistors of the current source are crossed.

Abstract: An integrated structure of a network of N add-compare-select (ACS) units associated with N states of a trellis of a Viterbi convolutive decoder. The ACS units are physically gathered by pairs juxtaposed to form two spaced apart parallel columns, each pair including two ACS units associated, respectively, with states 2n and 2n+1 modulo-N (n being a positive integer). Each of the two ACS units of the pair is coupled, for receiving two path metrics, to an ACS unit associated with one of states n and n+N/2 of a close pair and to an ACS unit associated with the other of states n and n+N/2 of a remote pair. The space between the two columns constitutes a common channel that includes the interconnections between remote pairs of units. The structure is implemented in a technology with at least three metallization layers and wherein the two ACS units of each pair are juxtaposed along the column height.

Abstract: A differential transconductance amplifier includes two first NPN transistors, whose bases receive a differential input voltage, and whose collectors are coupled to a first supply voltage through two respective first current sources; two second NPN transistors respectively coupling the emitters of the first transistors to a second supply voltage, and whose bases are coupled to the collectors of the respective first transistors through level shifters; and a resistive means coupled between the emitters of the first transistors. Each level shifter includes a third PNP transistor coupled between the collector of the respective first transistor and the base of the respective second transistor, and whose control terminal receives a constant bias voltage independent of the differential input voltage.

Abstract: The present invention relates to a device for limiting transient variations of a voltage for supplying a load from a dc/dc converter, including an input terminal, that receives the voltage provided by the converter, and connected to an output terminal of the device connected to the load; a first power transistor connected between a supply voltage of the converter and the output terminal; a second power transistor connected between the output terminal and the ground; and means for linearly and individually controlling each power transistor in case of an abrupt variation of the load.

Abstract: A sequential access memory working at the rate of a clock signal CK includes N register elements N, each storing an information bit. These register elements are divided into L groups, each comprising P elements that are series-connected and simultaneously activated or not activated (with P.times.L=N). The register elements of a given group are activated at least P times consecutively during a part of the time, and are not activated for the rest of the time. Accordingly, each group stores P consecutive information bits each from among the N bits arriving in serial form at the input of the memory. The advantage of the memory is that it enables a reduction in the dynamic energy consumption.

Abstract: A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).

Abstract: A fast operating, electronic overvoltage protection device intended for a power transistor having at least one control terminal of the MOS type is disclosed. The device comprises a Zener diode associated with the power transistor and integrated together therewith in a semiconductor substrate, and a second transistor connected to the power transistor into a Darlington configuration and also connected to the Zener diode. The protection from overvoltages provided by the device is very fast in operation, and can be implemented in integrated form at reduced cost and without introducing parasitic elements.

Abstract: The disclosure relates to memory cards having an electronic component housed in a cavity. The electronic support has a first base made of silicon, with a small thickness (between 50 and 100 microns) and a thicker (between 200 and 300 microns) second base, which is deposited on the first base and is formed by a material which is harder than silicon, such as cobalt, vanadium, titanium or ceramic.