Abstract: A device for decoding a data stream representing moving pictures encoded according to the MPEG standard in which a logical unit receives from an offset stage data containing the maximum number of bits in a variable length code returns the length of each decoded code to the offset stage, and produces a decoded value of each code. The logical unit includes a controller which controls at least two separate processing units, of which a first processing unit extracts the code length and addresses it to the offset stage, and a second processing unit decodes the codes.

Abstract: A process for the manufacturing of an integrated circuit having DMOS-technology power devices and non-volatile memory cells provides for forming respective laterally displaced isolated semiconductor regions, electrically insulated from each other and from a common semiconductor substrate, inside which the devices will be formed; forming conductive gate regions for the DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions. Inside the isolated semiconductor regions for the DMOS-technology power devices, channel regions extending under the insulated gate regions are formed. The channel regions are formed by an implantation of a dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that the channel regions are formed directly after the implantation of the dopant without performing a thermal diffusion at a high temperature of the dopant.

Abstract: The video memory requirement of an MPEG decoder, or of an SQTV processor, or of similar devices, wherein the storing of full pages or pixels or portions thereof is performed in decoding or in filtering noise, may be dynamically reduced by ADPCM recompressing and decompressing of the MPEG decoded digital data stream, before and after storing the data in the video memory, respectively. A particularly efficient and simple ADPCM compression method employs a differential variance estimator which, instead of processing bidimensional blocks of pels, instead processes blocks of pels all belonging to a same horizontal video line.

Abstract: The present invention relates to a linear regulator of a voltage for supplying a load, including circuitry for setting to partial stand-by the regulator as a response to a control signal supplied by the load setting of a linear regulator to stand-by the regulator in response to a control signal supplied by the load.

Abstract: An integrated structure is made in a chip of semiconductor material inside an insulated N type region extending from a surface of the chip. The structure comprises a Zener diode formed by a P type first region extending from the surface inside the insulated region and by a second region of type N extending from the surface inside the first region. These regions form between themselves a buried junction, in which the structure further includes a lateral bipolar transistor having an emitter region provided by the first region.

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract: A method is for reading a dynamic memory and a memory implementing the method. The memory includes at least one bit line, one word line, one storage cell accessible by the bit line and the word line, and one reference line, the storage cell enabling the storage of an initial potential representing a logic information. The method includes a step for the precharging of the bit line and the reference line, to carry the potential of these lines to the level of a reference potential that is different from the initial potential stored in the storage cell and a step for the selection of the storage cell to produce a modification of the potential of the bit line and thus create an initial difference between the potentials of the bit line and the reference line. It also includes a step for discharging the bit line and the reference line and a step for the production of an output signal whose state represents values of the discharge currents.

Abstract: A power amplifier device is disclosed, comprising a differential amplifier with determined transconductance followed by an intermediate amplification stage with a compensation capacitor between its output and its input and a push-pull output amplifier under low output impedance, for which the common point of connection between an upper stage and a lower stage gives an output of the device. A feedback loop between the output and the differential amplifier is provided in order to temporarily increase the transconductance of the differential amplifier at the passage of the conduction from one stage to the other stage of the push-pull amplifier.

Abstract: A charge pump includes a plurality of stages connected in series between a reference potential and an output terminal of the charge pump. The plurality of stages includes a first group of stages, proximate to the reference potential, and a second group of stages proximate to the output terminal of the charge pump. Each stage of the first group includes a pass-transistor with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor with a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and a positive voltage. Each stage of the second group includes a junction diode having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor having a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and the voltage supply.

Abstract: An electricity meter includes a first current probe, a first voltage probe and a display unit memorizing its contents. This meter comprises a fuzzy logic processor having a fuzzy logic decision-making computer with a non-volatile memory available to store membership functions corresponding to the first voltage and current probes and to store decision rules. The computer takes a decision, according to the rules, that is weighted by the membership functions and is aimed at incrementing the contents of the display unit. This meter has the particular feature, among others, by which it can be recalibrated on site.

Abstract: The power output of a static DC--DC converter employing a current mode PWM controller is controlled upon the varying of the switching frequency, by detecting the sawtooth signal produced by the local oscillator generating a DC signal with an amplitude inversely proportional to the frequency. The power output is controlled by alternatively clamping the output voltage of the error amplifier of the PWM controller at a voltage proportional to the amplitude of the DC signal, or by offsetting the signal present on the current sensing resistor by a voltage corresponding to the difference between a constant voltage and the DC signal.

Abstract: A method for the erasure of a non-volatile and electrically erasable memory in which the amplitude of the pulses that are sent to erase the memory varies as a function of the number of pulses previously sent. A circuit for the generation of erasure pulses of variable amplitude for a non-volatile and electrically erasable memory.

Abstract: A method and circuit to trim the internal timing conditions for a semiconductor memory device including a memory matrix and circuit portions for allowing reading of the data stored in the memory matrix wherein such circuit portions include an ATD generator detecting each transition of a plurality of address terminals of the memory device to produce an ATD synchronization signal, a sense amplifier which receives an equalization a signal EQU from a generator activated by the ATD signal, and output buffers enabled by an OUTLATCH signal produced by a generator receiving the ATD signal and the EQU signal. The length of the signals is automatically trimmed according to a corresponding length code contained in a portion of the memory device.

Abstract: A system for converting digital television signals encoded according to an MPEG standard into standardized analog video signals. The system includes means for generating graphic images and for inserting corresponding image signals in a decoded digital flow of main image signals, a digital decoding unit, and an analog coding unit. The digital decoding unit includes means for providing a flow of multiplexed image signals including a first flow of main image signals and of a second flow of image signals that contains, in addition to the main image signals, possible graphic image signals. The analog coding unit includes a demultiplexer of the flow of multiplexed image signals and two encoders. The two encoders respectively receive the first and second flows, and each respectively provide a digital flow of images encoded according to a color television standard to digital-to-analog converters respectively associated therewith, the digital-to-analog converters providing the standardized analog video signals.

Abstract: The present invention is a monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type, which cells allow the signal paths between signal lines of the elementary modules to be programmed and re-programmed. Preferably, the flash memory cells are Fowler-Nordheim Effect cells.

Abstract: An acceleration sensor is described which is formed by planar technology on a substrate. It includes a core of ferromagnetic material and, coupled conductively together by the core, a first winding adapted to be connected to a power supply and a second winding adapted to be connected to circuit means for measuring an electrical magnitude induced therein. The core has two suspended portions which are free to bend as a result of an inertial force due to an accelerative movement of the sensor itself. The bending causes lengthening of the core and hence a variation in the reluctance of the magnetic circuit. If a constant current is supplied to the first winding, a voltage is induced in the second winding as a result of the variation in the magnetic flux caused by the variation in reluctance.

Abstract: A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.

Abstract: A servo-demodulator for a pair of alternating signals generated by a magnetic disc read head and indicative of the position of the read head in relation to the center of a recorded track. The servo-demodulator comprises a peak detector for successively and individually sampling the amplitude of each of a plurality of peaks of the pair of alternating signals, and a capacitor periodically connected to the output of the peak detector by a control logic for deriving a weighted average of the various successively sampled amplitudes. In this manner, the control logic obtains an averaged measure of amplitude with high immunity to noise.

Abstract: A structure is disclosed which comprises a metal plate, a chip of a semiconductor material attached to the plate, terminal leads, interconnection wires between the leads and the metallized regions of the chip, and a polymer body encapsulating all this with the exception of a surface of the plate and part of the leads. To achieve improved bond between the polymer and the metal, predetermined areas of the plate and the leads have a higher roughness than 1 (R.sub.a .gtoreq.1 .mu.m).

Abstract: A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.