Abstract: This invention relates to an evaporation installation of the type including a frame rotatably hanging around a first vertical shaft and supporting at least three arms for receiving at least three concave supports of wafers to be processed, rotatably mounted around secondary shafts supported by the arms, the arms being inscribed in a cone which is coaxial to the first shaft so that the secondary shafts have a rotating motion in a plane perpendicular to the vertical shaft. The supports are disposed so as to overlap.

Abstract: A process for forming a microtip cathode structure on a field emission display panel which avoids the need of vacuum depositing a lift-off layer for the microtip deposition overstructure in specially equipped reactors to accomplish a deposition at a grazing angle, by co-patterening the lift-off layer together with an underlying metal grid layer using a succession of different etching steps through the openings of a grid definition mask. According to an embodiment, nickel is used as lift-off material and is either wet-etched or sputter-etched before performing a plasma etch of the underlying grid metal layer. According to an alternative embodiment, the masking resist layer is used as lift-off material.

Abstract: The present invention relates to a voltage regulator, including at least two input terminals for receiving, each, an independent supply voltage, and including a means for automatically selecting the highest supply voltage from among the voltages present at the input terminals, and a means for insulating the supply terminal associated with the lowest voltage from the rest of the circuit, these means introducing a very low voltage drop between the input terminal at the highest voltage and an output terminal of the regulator.

Abstract: In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.

Abstract: A monolithic component for protection against over-currents liable to occur on a line in series with which is connected a detection resistor, comprises a first cathode-gate thyristor associated with an avalanche diode and a second anode-gate thyristor of the gate triggering type or forward breakover type, its breakover voltage being substantially equal to the avalanche voltage of the avalanche diode.

Abstract: The present invention relates to a device for starting and supplying a fluorescent tube, including a resonant system connected to the tube and to a rectified supply circuit with a switch in series. A first detector controls the switch to turn off when the current provided by the supply exceeds a determined threshold; and a second detector controls the switch to turn on for each transition through zero of the voltage on a node of the resonant system and for each transition through a minimum of this voltage.

Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main thyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.

Abstract: Disclosed is a device for controlling the operation of a machine comprising at least one measurement sensor, one circuit to control this operation as a function of a signal sent out by the sensor and one input for the supply of alternating electrical power to the machine. This control device includes a memory known as a program memory containing a set of membership functions, a set of decision rules and a fuzzy logic program, a fuzzy logic processor used to prepare a decision signal that depends on the signal sent out by the sensor, on these membership functions and on these rules all at the same time and that is used to activate the operation of this machine with this decision signal, and in the program memory, additional membership functions that take account, as variables, of the signals available at the electrical supply input and of the rules that take account of these membership functions. The disclosure can be applied to devices for the control of electrical machines.

Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.

Abstract: A method of depositing a layered dielectric structure to improve the planarity of electronic devices which include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. The bit lines are isolated from one another by a layered dielectric structure to provide a planar architecture onto which an optional conductive layer may be deposited. The dielectric structure is formed from a highly planarizing dielectric layer of the SOG type spun over a first insulating dielectric layer and solidified by means of a thermal polymerization process. After solidifying the dielectric layer, it is subjected to a rapid thermal annealing treatment.

Abstract: A method and apparatus for sequencing an integrated circuit which receives an external clock signal consists of the use of an internally generated random clock signal and of the use of either of these clock signals depending on the instruction to be performed.

Abstract: In a switched operational amplifier including a differential input stage and at least a second output stage, the compensation capacitor commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with a switching circuit. The switching circuit is controlled by the same control phase that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.

Abstract: The invention relates to a multitask processing system including a data bus and a command bus. Each one of a plurality of operators is provided to perform a processing determined by an instruction and is likely to issue a command request in order to receive an instruction from the command bus and to issue a transfer request on response to an acknowledgment of the command request, in order to receive or provide data being processed, through the data bus. A memory controller arbitrates the transfer requests and manages the data transfers on the data bus between the operators and a memory. A sequencer arbitrates the command requests, determines instructions to provide the operators with, and manages the instruction transfer through the command bus.

Abstract: The present invention relates to a device for controlling a composite bridge including two anode-gate thyristors, the cathodes of which are connected together to a positive output terminal, the gates of the two thyristors being interconnected. The device includes a single-throw switch, controllable to be turned off and on, connected on the one hand to the two thyristors and on the other hand to a reference potential, and control means to turn on the switch only in a predetermined voltage range around the zero voltage of an a.c. voltage of the composite bridge.

Abstract: A method for calibrating the temperature of an epitaxy reactor includes the steps of preparing a reference wafer having undergone on at least one of its surfaces an implant of a doping followed by an activation annealing to form a diffused layer; measuring the sheet resistance of the diffused layer at one point on the surface of the wafer; placing the reference wafer in the epitaxy reactor, the reactor being set at a desired temperature and having a neutral gas flowing therein; and measuring the sheet resistance at the same point and calculating the difference between the two values of sheet resistance, this difference representing the thermal cycle undergone by the reference wafer during its stay in the epitaxy reactor.

Abstract: A CMOS twin-tub negative voltage switching architecture is for a non-volatile memory device and includes a negative voltage multiplier for generating a increased voltage value starting from a single main power supply. A voltage regulator feedback is connected to the voltage multiplier for regulating the generated negative voltage value; and a plurality of independent switch circuits each one receiving as an input the negative voltage value and producing as an output a predetermined local negative voltage.

Abstract: A method for adjusting the gain or the sensitivity of a lateral component formed in the front surface of a semiconductor wafer, having a first conductivity type, includes not doping or overdoping, according to the first conductivity type, the back surface when it is desired to reduce the gain or sensitivity of the lateral component, and doping according to the second conductivity type, the back surface, when the gain or the sensitivity of the lateral component is to be increased.

Abstract: An integrated circuit data processing structure and method for performing a discrete cosine transform (DCT) makes the correspondence between a table f(x,y) of N.times.N data and a table F(u,v) of N.times.N coefficients according to the following relation: ##EQU1## The innovative structure uses: a memory containing a data table;a memory of the productsP=.vertline.cos[n(x,u).pi./2N].multidot.cos[n(y,v).pi./2N].vertline., with:p(x,u)=Sgn[p(x,u)].multidot..vertline.cos[n(x,u).pi./2N].vertline.p(y,v)=Sgn[p(y,v)].multidot..vertline.cos[n(y,v).pi./2N].vertline.where n(x,u) and n(y,v) are integers ranging from 1 to N-1;a table of the signs of p(x,u) and p(y,v) and values of n(x,u) and n(y,v) addressing the product memory (3);a coordinate generator sequentially providing value pair (u,v) and, for each pair (u,v), all the values of pair (x,y);a multiplier calculating the product of P by a data combination of the data memory; andan accumulator of the results of the multiplication.

Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage and an amplifier output stage connected serially together to receive an input signal on at least one input terminal of the amplifier and generate an amplified signal on an output terminal of the amplifier. Provided between the input and output stages is an intermediate node which is connected to a compensation block to receive a frequency-variable compensation signal therefrom. The compensation block is coupled with its input to the input terminal of the amplifier. The compensation block is connected to receive at least the feedback signal. Preferably, the compensation signal is variable as a function of a gain value which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value.

Abstract: The present invention concerns a transmission circuit of an audio/video data bus that includes a clamp connected between first and second output terminals of the transmission circuit; biasing networks for respectively biasing the output terminals during one operational mode of the transmission circuit; and switched biasing networks for respectively biasing the output terminals during a second operational mode of the transmission circuit; the switched biasing networks being controlled by a digital input signal, wherein a circuit is provided for protecting the clamp from short circuit connections to the transmission circuits voltage supply rails.