Abstract: A power integrated circuit including a substrate of semiconductor material having a first conductivity type on which is formed a first epitaxial layer of the same conductivity type. In a first portion of the first epitaxial layer are formed first and second diffused regions having respectively first and second conductivity type. The first and the second diffused regions are isolated from a power stage included partially in a second portion of the first epitaxial layer by an annular region having the second conductivity type. Over the first epitaxial layer is formed a second epitaxial layer having the first conductivity type in which are extended the first and the second diffused regions to permit forming a control circuitry for the power stage.

Abstract: A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer.

Abstract: Process for producing metrological structures particularly for direct measurement of errors introduced by alignment systems, whose peculiarity consists in performing, on a same substrate, metrological alignment markings and processed alignment markings according to arrays of preset numerical size.

Abstract: Disclosed is a memory read circuit with a device to limit the precharging of the bit lines. The circuit includes a portion forming a current mirror and providing furthermore for a controlled precharging of the bit line and of the reference line in limiting the precharging potential to a borderline value referenced with respect to the ground. The circuit may be applied to non-volatile (EEPROM, Flash EPROM) memories, and especially memories supplied with low voltages.

Abstract: This invention relates to a device for protecting a circuit against voltage surges, including a MOS transistor of a first type connected to first and second supply terminals by its source and its drain, respectively; a MOS transistor of a second type connected between the second supply terminal and the gate of the first type transistor, by its source and its drain, respectively; and a capacitor having a first terminal connected to the first supply terminal and a second terminal connected to the gate of the second type transistor.

Abstract: A matrix computation processor comprises a control unit and a data memory, and a plurality of computation units. The plurality of computation units are controlled by the control unit by means of a control bus comprising: a first group of wires connected to the plurality of computation units conveying a common instruction to the plurality of computation units; and a plurality of second groups of at least one wire, each being connected respectively to one of the plurality of computation units, conveying an instruction complement specific to each computation unit of the plurality of computation units.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: Disclosed is a device including three registers, one input terminal to receive pieces of binary data to be stored in these registers, a multiplication circuit enabling the performance of a multiplication operation between two pieces of data stored in two of the registers, a first addition circuit enabling the performance of an addition operation between a piece of data stored in the second register and a piece of data produced by the multiplication circuit, a subtraction circuit placed between the second register and the addition circuit, a delay cell and a second addition circuit placed between the first addition circuit and the input of the second register, multiplexing circuitry making it possible to provide the contents of the second register or a permanent logic state to one input of one of the addition circuits, to connect another input of the addition circuit to an output of the multiplication circuit and to connect an output of the addition circuit to an input of the second register.

Abstract: The present invention relates to an integrated circuit adapted to perform the function of a diode of the DIAC type, the circuit having an input terminal and an output terminal. The circuit includes a first input transistor having a first terminal connected to a fixed voltage reference, a second terminal, and a control terminal coupled to the input terminal of the circuit. The circuit further includes second and third transistors in a current mirror configuration, each having a first terminal for coupling to the input terminal of the circuit, and a second terminal, and associated control terminals connected together and coupled to the second terminal of the first input transistor, the second terminal of the second transistor being connected to the control terminal of the first transistor.

Abstract: The present invention relates to a bidirectional breakover component including a lightly-doped N-type substrate, an upper P-type region extending over practically the entire upper surface of the component except its circumference, a lower P-type uniform layer on the lower surface side of the component, substantially complementary N-type regions respectively formed in the upper region and in the lower layer, a peripheral P-type well, an overdoped P-type region at the upper surface of the well, and lightly-doped N-type regions between the circumference of the upper region and the well.

Abstract: A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block connected to an input terminal for memory address line transition signals. The delay block drives a counter which feedback controls the discharge through a combinational logic circuit connected to the output terminal of the programmable delay block. A logic output circuit, connected to the output terminal of the delay block and to the counter, generates the timing signals.

Abstract: A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub except in the region in which the zone extends.

Abstract: A synchronization circuit for electronic devices and components, being of the type which includes an internal synchronization signal generator and an input/output terminal whereat an external synchronization signal can be received. The synchronization circuit further includes a comparator for receiving both synchronization signals and having a control output for supplying a terminal with the signal corresponding to the master/slave mode of operation of the synchronization circuit. A method of generating and supplying a synchronization signal to a plurality of electronic devices being operated as slave devices to a synchronization circuit acting as the master device is also provided.

Abstract: A monolithic component including, in an N-type lightly-doped substrate of a semiconductor wafer, two portions separated by a P-type insulating wall. A first portion of the two portions includes a high voltage lateral component, a layer of which substantially corresponds to the thickness of the wafer. The second portion includes logic circuit components. A rear surface of the substrate includes a P-type layer coated with a metallization. The insulating wall is in electrical contact with a low voltage terminal of the high voltage lateral component, such as the gate region of a thyristor. The logic portion includes at least one vertical component.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: Disclosed is a method for the fabrication of an extrinsic base of an NPN transistor using high frequency bipolar technology. According to the method, using a doping of the extrinsic base of the transistor by ion implantation, the amorphous crystal lattice is recrystallized by very high-speed thermal annealing before the dopants of the extrinsic base are diffused in the epitaxial layer.

Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

Abstract: The present invention relates to a circuit for processing vertical synchronization logic signals of positive or negative polarity. Based on signals locating, on the one hand, the presence of the beginning of a pulse and, on the other hand, the rising and falling edges in the synchronization signals, a brief pulse is provided in a signal generated by a one-shot. This pulse induces the generation of edges in signals controlling a latch which generates a logic detection signal. According to the polarity of the received signals, the latch is set or reset and the state of the detection signal indicates the polarity of the synchronization signals.

Abstract: To increase the integration density of an EEPROM type memory, it is chosen to do without the selection transistor. To then arrive at a selection operation in erasure, programming or reading modes, it is chosen to apply negative voltages or voltages with a value half that of a programming voltage (VPP) to certain connections (with r' different from r) of the memory.

Abstract: The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives also addresses of the control bits of a control word assigned to a word to be protected. It can be shown that this mode of action provides greater security through the use of a decision table made in wired circuit form as well as greater flexibility through the programmable quality of the control words assigned to each memory word to be controlled.