Patents Assigned to SGS-Thomson Microelectronics S.A.
  • Method for the correction of a message in an installation
    Patent number: 6212658
    Abstract: A method for the accurate transmission of a message between a transmitter and a receiver that are connected to a transmission line supplied by the mains system. The method includes means for distinguishing between errors caused by line attenuation and errors caused by parasitic pulses. Once the cause of the errors is known, messages can be sent at appropriate different transmission rates and, if necessary, synchronously with the frequency of the mains system.
    Type: Grant
    Filed: September 2, 1994
    Date of Patent: April 3, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Maurice Gilbert Le Van Suu
  • Device for correcting the color of a television signal according to NTSC standard
    Patent number: 6211923
    Abstract: A device corrects the chrominance parameters transmitted by a chrominance subcarrier of a television signal, by shifting the phase of two demodulation signals an angle, which depends upon the phase of the chrominance subcarrier. The demodulation signals are obtained from a phase-locked loop including a resistive and capacitive network having two outputs that differ by 90° with respect to each other. The device may include circuitry for individually shifting the phase of each signal provided by the RC network by adding to each signal a fraction of the other signal provided by the RC network. The fractional coefficients may be opposite to each other and depend upon the phase of the chrominance subcarrier.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: April 3, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Yann Desprez-le Goarant
  • Data reading path management architecture for a memory device, particularly for non-volatile memories
    Patent number: 6212096
    Abstract: A data reading path management architecture for a memory device, particularly of the non-volatile type, comprising a memory matrix and data sensing means that are adapted to receive the data of the memory matrix for reading, which has the particularity that the memory matrix is divided into at least two half-matrices. Each one of the two half-matrices has a reference line that is adapted to constitute a reference for reading the other half-matrix. The data sensing means receive the data from one half-matrix and the reference from the other half-matrix and are adapted to transmit, according to a control timing, the data on an internal bus.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: April 3, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Luigi Pascucci
  • Device of adjustment of the charge current of a storage capacitor
    Patent number: 6212082
    Abstract: The present invention relates to a supply circuit with a storage capacitor and a method of control of this circuit including, across a rectifying bridge, a storage capacitor associated with a charge path and with a discharge path, in which the duration of charge periods of the storage capacitor is set, at least at steady state, to a predetermined duration.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: April 3, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Alain Bailly
  • Device for demultiplexing information encoded according to a MPEG standard
    Patent number: 6205180
    Abstract: A device for demultiplexing data encoded according to a MPEG standard in the form of a data flow including system and picture packets. The device includes means for independently organizing, according to the nature (system packet, video packet, audio packet, etc.) of the data included in the packets, the storing of the data in various registers, some of the registers being accessible in read mode by a RAM and other registers being accessible by a microprocessor.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: March 20, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Denis Dutey
  • Set of two memories on the same monolithic integrated circuit
    Patent number: 6205512
    Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: March 20, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Alessandro Brigati, Jean Devin, Bruno Leconte
  • Method and device for setup of clipping noise of a multicarrier modulation
    Patent number: 6198778
    Abstract: The present invention relates to a method for setup of a signal in multicarrier modulation, including clipping the signal, in amplitude, with respect to a threshold value, and of reinjecting, with a delay and on the signal to be set up, a clipping noise redistributed, at least partly, outside the useful slip of the signal in multicarrier modulation.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: March 6, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Denis J. G. Mestdagh
  • Apparatus for postponing processing of interrupts by a microprocessor
    Patent number: 6192441
    Abstract: This device controls the interrupts of a microprocessor based on events occurring in at least one entity associated with this microprocessor. The device organizes the storage of words representative of at least an origin and a type of the interrupt issued by the entity. The interrupts from the entity are stored in an area of a memory. When there is more than one entity, each entity has an area of memory allocated to it. The microprocessor can access these memory areas and process the interrupts. An indicator is also provided so that the device can tell when a memory area has become full.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: February 20, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Claude Athenes, Pascal Moniot
  • High voltage capacitor
    Patent number: 6188121
    Abstract: A high voltage capacitor, integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: February 13, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Livio Baldi, Paolo Ghezzi, Alfonso Maurelli
  • Method and apparatus for storing one or more natural membership functions
    Patent number: 6188998
    Abstract: In a method, according to the invention, of storing one or more natural membership functions of respectively one or more natural variables being each defined within a natural universe of discourse having a lowest natural value and a highest natural value, the natural membership functions are normalized through respective normalization coefficients so that they are defined within the same predetermined absolute universe of discourse having a lowest absolute value and a highest absolute value, thereby obtaining one or more absolute membership functions, respectively, and said absolute membership functions and said normalization coefficients are stored, taking account that identical absolute membership functions are stored only once.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: February 13, 2001
    Assignees: SGS-Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Antonino Cuce', Matteo Lo Presti
  • Circuit for the management of memories in a multiple-user environment with access request and priority
    Patent number: 6189075
    Abstract: A multiple-user processing system exchanges data elements with a central memory by a request system managed by a management circuit. The system furthermore has available a buffer memory to regulate the flow of information from the central memory.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: February 13, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Josè Sanches
  • Method for final passivation of integrated circuit
    Patent number: 6187683
    Abstract: A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: February 13, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Giorgio De Santi, Luca Zanotti, Giuseppe Crisenza
  • Bidirectional charge pump generating either a positive or negative voltage
    Patent number: 6184741
    Abstract: A charge pump comprises at least one charge pump stage including a first diode having an anode and a cathode, and a capacitor having a first plate connected to the cathode of the diode and a second plate connected to a clock signal that periodically varies between a reference voltage and a supply voltage, the anode of said diode forming a first terminal of the charge pump. The charge pump further comprises a second diode having an anode connected to the cathode of the first diode and a cathode forming a second terminal of the charge pump, first switching means for selectively coupling the first terminal of the charge pump to the voltage supply and second switching means for selectively coupling the second terminal of the charge pump to the reference voltage.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: February 6, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Andrea Ghilardelli, Giovanni Campardo, Jacopo Mulatti
  • Method for manufacturing a well isolation bipolar transistor
    Patent number: 6184102
    Abstract: The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a base contacting region. A second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter, to form an emitter contacting region.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: February 6, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Yvon Gris
  • Multiple layer interconnects with low stray lateral capacitance
    Patent number: 6180520
    Abstract: The present invention relates to an interconnect structure wherein the upper surface of the first interconnect level is a tungsten layer, portions of the first interconnect level are insulated from one another by an insulator of the SOG type, portions of a second interconnect level are connected to portions of the first interconnect level by conductive pads formed in openings of an insulating layer, at least the lower part of which is of the SOG type, the walls and the bottom of the openings are covered with a thin titanium layer, and the openings are filled with a conductive material selected in the group including Al, Cu and aluminum alloys such as silicon, copper, and titanium alloys.
    Type: Grant
    Filed: April 8, 1997
    Date of Patent: January 30, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Michel Marty, G{acute over (e)}rard Passemard, Graeme Wyborn
  • Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method
    Patent number: 6180442
    Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: January 30, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Yvon Gris
  • Method and device for the incremental reading of a memory
    Patent number: 6178490
    Abstract: Disclosed is a method and a device to improve the data output speed of a memory associated with a central processing unit of a microcomputer, should the reading be done at consecutive addresses of the memory in the mode known as the “burst read” mode. The address register is of the type with incrementation controlled by a sequencing circuit. The read register is followed by a data register which records the contents of the read register so as to free this read register to record the contents of the memory cells that are selected by the incremented address.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: January 23, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jean-Marie Gaultier, G{acute over (e)}rard Silvestre De Ferron
  • Adaptive intrafield reducing of Gaussian noise by fuzzy logic processing
    Patent number: 6175657
    Abstract: The level of Gaussian noise in a memory field being scanned by rows is reduced by reconstructing each pixel by fuzzy logic processors. The processors process the values of pixels neighboring the pixel being processed and belonging to a processing window defined by the last scanned row and the row being scanned, thus minimizing the memory requirement of the filtering system to a single row. The system performs an adaptive filtering within the current field itself and does not produce “edge-smoothing” effects as in prior adaptive filtering systems operating on consecutive fields.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: January 16, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Massimo Mancuso, Viviana D'Alto, Daniele Sirtori, Rinaldo Poluzzi
  • Voltage regulator for programming electrically programmable non-volatile memory cells in a cell matrix
    Patent number: 6175521
    Abstract: A voltage regulator for programming electrically programmable non-volatile memory cells in a cell matrix that is divided in segments. The voltage regulator includes an amplifier stage connected and powered between a first reference voltage and a second reference voltage and having a first input terminal connected to a voltage divider of the first reference voltage, an output terminal connected to the control terminal of a MOS transistor which has a conduction terminal connected to the memory cells through a programming line, and a second input terminal connected to the programming line, and connected to the output terminal in a feedback loop. The voltage regulator includes an input circuit portion made up of active elements and inserted in turn between the first and second reference voltages.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: January 16, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Luigi Pascucci, Marco Fontana
  • Booster circuit
    Patent number: 6175262
    Abstract: The present invention relates to a booster circuit including a first P-MOS transistor, the source of which is connected to a high voltage line; a second N-MOS transistor, the drain of which is connected to a first supply potential and the source of which is connected to the drain of the first transistor; a first capacitor connected between the gate of the first transistor and a terminal of reception of a first clock signal; a second capacitor connected between the gate of the second transistor and the reception terminal for the first clock signal; a third capacitor connected between the drain of the first transistor and a reception terminal for a second clock signal, complementary to the first clock signal; two precharge diodes the first capacitor from the high voltage line; and one precharge diode for the second capacitor.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: January 16, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Laurent Savelli, David Novosel