Abstract: A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

Abstract: The present disclosure relates to a method for treating a wafer surface. By controlling the gas composition at each stage of the treatment process, and corresponding processes of heating and annealing, and cooling and thinning by oxidation, the final wafer is enabled to have a surface roughness of less than 5 ?. This effectively reduces the cost of the final treatment process and has good application prospects.

Abstract: The present application provides a process of surface treatment of a silicon-on-insulator (SOI) wafer comprising: providing a SOI wafer comprising a back substrate, a top silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 ?; conducting a first planarization to a surface of the top silicon layer by conducting a batch annealing process at a first target temperature, and conducting a second planarization to a surface of the top silicon layer by conducting a rapid thermal annealing process at a second target temperature. The present application combines the batch annealing process and the rapid thermal annealing process to optimize the SOI wafer, especially the surface roughness of the SOI wafer. The SOI wafer planarized by the two thermal annealing processes has a good surface roughness of the top silicon layer which satisfies process requirements.

Abstract: A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

Abstract: The present disclosure provides a gallium oxide semiconductor structure, a vertical gallium oxide-based power device, and a preparation method. An unintentionally doped gallium oxide layer (110) is transferred to a highly doped and highly thermally conductive heterogeneous substrate (200) by bonding and thinning; then a heavily doped gallium oxide layer (120) is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure including the heterogeneous substrate (200), the gallium oxide layer (110), and the heavily doped gallium oxide layer (120) stacked in sequence. In the vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure, the gallium oxide layer (110) is a thicker intermediate layer and a carrier concentration of the gallium oxide layer (110) is less than that of the heavily doped gallium oxide layer (120).

Abstract: The invention provides a measuring method of resistivity of a wafer, comprising: choosing a wafer to be measured, conducting a thermal treatment for the wafer to remove a thermal doner in the wafer, conducting an oxidation process for the wafer to form an oxidized surface on the wafer, and measuring resistivity of the wafer. In the method, firstly, the wafer is oxidized to get the oxidized surface, so as to restrict surface variation when placing the wafer in a later process. Therefore, the resistivity measurement of the wafer surface only slightly varies.

Abstract: The present application provides a method for verification of conductivity type of a silicon wafer. The method comprises measuring the resistivity of the silicon wafer to obtain a first resistivity, placing the silicon wafer under atmosphere of air for a predicted time period, measuring the resistivity of the silicon wafer to obtain a second resistivity, and determining conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity. The method can be applied to a silicon wafer having a high resistivity such as higher than 500 ohm-cm to rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.

Abstract: A cryogenic memory cell and a memory device are provided. The cryogenic memory cell includes a spin moment transfer device. The spin moment transfer device converts a write current into a spin polarization current and changes a magnetic polarization direction under the action of the spin polarization current to achieve write storage of 0 and 1. The cryogenic memory cell also includes a nano-superconducting quantum interference device; a ground terminal of the nano-superconducting quantum interference device is in common-ground connection with a ground terminal of the spin moment transfer device, and the nano-superconducting quantum interference device undergoes a magnetic flux change under the action of a change in the magnetic polarization direction of the spin moment transfer device, thereby switching between a superconducting state and a non-superconducting state under a read current bias, to achieve read-out of 0 and 1.

Abstract: A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.

Abstract: The present invention provides a graphene structure having graphene bubbles and a preparation method for the same. The preparation method comprises: providing a substrate; forming a hydrogen terminated layer on a top surface of the substrate and a graphene layer disposed on a top surface of the hydrogen terminated layer; and placing a probe on the graphene layer and applying a preset voltage to the probe, to excite a part of the hydrogen terminated layer at a position corresponding to the probe to convert into hydrogen, the hydrogen causing the graphene layer at a position corresponding to the hydrogen to bulge, so as to form a graphene bubble enveloping the hydrogen.

Abstract: The present disclosure provides a method for preparing patterned graphene, and the method includes using a silicon carbide base as a solid-state carbon source, decomposing the silicon carbide under the action of high temperature and catalyst, to directly grow graphene on an insulating substrate. Through a first patterned trench and a second patterned trench in an accommodating passage, the pattern of the formed graphene can be directly controlled. Therefore, the present disclosure can accurately locate the position of the patterned graphene on the insulating substrate, it does not require transferring the graphene one more time, thereby avoiding contaminating the graphene and damaging its structure, and there is no need for photo-lithography, ion etching and other processes to treat the graphene in order to obtain patterned graphene, which further avoids damages to the graphene.

Abstract: A micro-power wireless access method and apparatus for the Internet of things for power transmission and transformation equipment involves a time synchronization process, a traffic channel access process, a control channel configuration information access process, and a control channel burst information access process. In the time synchronization process, an aggregation node determines a delay parameter and other parameters based on a timeslot in which traffic information randomly transmitted by a sensing terminal is located, and the sensing terminal adjusts transmission time of a corresponding frame based on the parameters. The traffic channel access process adopts a mode in which one-way reporting is mainly used, to minimize working time of a sensor. The present disclosure realizes limited two-way communication on a control channel, supports configuration of a sensor cycle, a threshold, and other parameters, and supports a retransmission mechanism on the control channel for important alarm information.

Abstract: The invention provides a method of detecting crystallographic defects, comprising: sampling wafer of an ingot in complying with a predetermined wafer sampling frequency; identifying crystallographic defects of the wafer to show the crystallographic defects of the wafer; characterizing observation of the crystallographic defects of the wafer and extracting a value characterizing the crystallographic defects; through a result of characterizing the crystallographic defects, obtaining a radial distribution of density of the wafer and categorizing the crystallographic defects; and obtaining an isogram of the crystallographic defects of the wafer to show a crystallographic defect distribution of the whole ingot according to the value characterizing the crystallographic defects and categories of the crystallographic defects.

Abstract: A phase change material, a phase change memory cell, and a preparation method thereof. The phase change material comprises elements tantalum, antimony and tellurium, the phase change material having a chemical formula of TaxSbyTez, wherein x, y, and z represent atomic ratios of the elements respectively; and 1?x?25, 0.5?y:z?3, and x+y+z=100. The phase change thin film material TaxSbyTez has a high phase change speed, outstanding thermal stability, strong data retention capability, a long cycle life, and a high yield. Ta5.7Sb37.7Te56.6 has ten-year data retention capability at 165° C.; and applying same in a device cell of a phase change memory achieves an operating speed of 6 ns and endurance of more than 1 million write-erase cycles. The crystal grains of the phase change material TaxSbyTez of the present disclosure are small, and after annealing treatment at 400° C. for 30 minutes, the grain size is still smaller than 30 nm.

Abstract: The present application provides a method for characterizing defects in silicon crystal comprising the following steps: etching a surface of the silicon crystal to remove a predicted thickness of the silicon crystal; conducting a LLS scanning to a surface of the etched silicon crystal to obtain a LLS map of the surface, a LSE size of defects, and defect bulk density; based on at least one of the LLS map of the surface, the LSE size of defects and the defect bulk density, determining a type of defect existing in the silicon crystal and/or a defect zone of each type of defect on the surface. By applying the method, the characterizing period and the characterizing cost can be reduced, plural defects such as vacancy, oxygen precipitate and dislocation can be characterized simultaneously, the characterizing accuracy can be enhanced, and the defect type and the defect zone can be determined with high reliability.

Abstract: The present invention provides a high-throughput vapor deposition apparatus and a vapor deposition method. A rotary workbench (2) is located in a reaction chamber (1); a gas introduction device (3) is located in the reaction chamber (1) and above the rotary workbench (2); a plurality of through holes (31) is provided on the gas introduction device (3); a gas isolation structure (4) divides an upper chamber (11) into an isolation gas chamber (111) and a reaction gas chamber (112) which are isolated from each other; an isolation gas is introduced into the isolation gas chamber (111) via an isolation gas introduction channel (5), and a reaction gas is introduced into the reaction gas chamber (112) via a reaction gas introduction channel (6), for carrying out thin film deposition on an area of a substrate corresponding to the reaction gas chamber (112).

Abstract: A method of making a silicon on insulator structure comprises: providing a bonded structure, the bonded structure comprises the first substrate, the second substrate and the insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a first film; at a first temperature, performing a first etching to etch the first film to remove a first thickness of the first film; at a second temperature, performing a second etching to etch the first film to planarize the first film and remove a second thickness of the first film, the first temperature being lower than the second temperature, the first thickness being greater than the second thickness, and a sum of the first thickness and the second thickness being a total etching thickness of the first film.

Abstract: A superconducting integrated circuit design method based on placement and routing by different-layer JTLs comprises: cutting a bias line at a cell data interface of a cell library, and reserving a position of a via; placing and arranging cells on a logic cell layer according to a schematic circuit logic diagram; connecting clock lines of each of the cells by using a JTL and a splitter of the logic cell layer; and performing data connection on each of the cells by using JTLs of a transverse JTL routing layer and a longitudinal JTL routing layer which are not in the same layer as the logic cell layer, wherein the JTL of the transverse JTL routing layer is used as a transverse routing cell for data between the cells, the JTL of the longitudinal JTL routing layer is used as a longitudinal routing cell for data between the cells.

Abstract: The present invention provides a laser, including: a medium, having a ground state, an intermediate state, and an excited state in ascending order of energy; an excitation system, configured to excite electrons in the medium from the ground state to the intermediate state; and an excitation laser, configured to drive electrons in the intermediate state at different spatial positions in the medium to the ground state through a stimulated emission process with a fixed phase relationship, to generate a laser with a shorter relative wavelength. Due to the use of an excitation laser to drive electrons from the intermediate state, the photons generated by the stimulated emission have coherence, thereby forming a laser.

Abstract: The present disclosure provides a method and system for improving a counting rate of a superconducting nanowire single photon detector. The method includes: coupling an electrical attenuator in series with an output end of the superconducting nanowire single photon detector; the electrical attenuator includes an input end and an output end, and the input end of the electrical attenuator is coupled with the output end of the superconducting nanowire single photon detector. The present disclosure couples the electrical attenuator in series with the output end of the superconducting nanowire single photon detector. Since the configuration of the electrical attenuator is a resistor network, it can act as a series resistor and can also reduce the response pulse amplitude of the superconducting nanowire single photon detector. The present disclosure can improve the counting rate of the superconducting nanowire single photon detector, while keeping the detection efficiency high.