Abstract: The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance.

Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.

Abstract: The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices.

Abstract: The present invention discloses an SOI CMOS device having a vertical gate structure, comprising: an SOI substrate, and an NMOS region and a PMOS region grown on the SOI substrate, wherein the NMOS region and the PMOS region share one vertical gate region, said vertical gate region lying in the same plane as the NMOS region and the PMOS region and between the NMOS region and the PMOS region; a gate oxide layer is arranged between the vertical gate region and the NMOS region for isolation; and a gate oxide layer is arranged between the vertical gate region and the PMOS region for isolation. The present invention occupies small area, contains less pattern layers, requires a simple process, has an open body region that can completely avoid the floating effect of the traditional SOI CMOS device, and is convenient to parasitic resistance and capacitance tests.

Abstract: A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.

Abstract: A method to create piezoresistive sensing elements and electrostatic actuator elements on trench sidewalls is disclosed. P-type doped regions are formed in the upper surface of an n-type substrate. A trench is formed in the substrate (e.g. by DRIE process) intersecting with the doped regions and defining a portion of the substrate which is movable in the plane of the substrate relative to the rest of the substrate. Then diffusion of P-type dopant into the trench side-walls creates piezoresistive elements and electrode elements for electrostatic actuation. Owing to the intersection of two doped regions, there are good electrical paths between the electrical elements on the trench side-walls and the previously P-type doped portions on the wafer surface. The trench intersects with insulating elements, so that insulating elements mutually insulate adjacent electrical elements. P-n junctions between the electrical elements and the substrate insulate the electrical elements from the substrate.