Abstract: A method is provided of fabricating a thin film transistor semiconductor film of polycrystalline silicon on a transparent substrate suitable for the manufacture of a liquid crystal display. A film of substantially amorphous silicon is placed on the transparent substrate. Suspended in the amorphous silicon are small silicon seed crystals. As the amorphous silicon is annealed, crystal grains, begun from the seed crystals, are formed in the resulting polycrystalline silicon. The seed crystals help regulate the annealment process, and reduce process dependence on precision deposition and heating methods. The use of seed crystals also helps ensure that crystal grains are both large and consistent in size. Large grains promote to production of TFTs with high electron mobility and uniform performance across the entire LCD.

Abstract: A testing and diagnostic mechanism includes an external bus master allows access of virtually all internal registers on an integrated circuit, and allows the on-chip SRAM/DRAM controllers to access external memory.

Abstract: A method is provided for forming intermediate levels in an integrated circuit dielectric during a damascene process using a hard mask layer to transfer the pattern of a photoresist mask having at least one intermediate thickness. The dielectric is covered with a hard mask layer, and the hard mask layer is covered with the photoresist mask. The photoresist mask pattern is transferred into the hard mask pattern so that the hard mask pattern has at least one intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the hard mask pattern. The hard mask pattern is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is etched to a second depth, less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias.

Abstract: A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed.

Abstract: A single port antenna connector assembly, mateable with either a retractable antenna or a hardline connector, is provided. When the antenna connector is mated with the connector assembly, it engages a signal contact supplying an antenna signal. When the hardline connector is mated, it engages a signal contact supplying a conductive signal to test equipment, or to an auxiliary antenna. The signal contacts have different positions in the assembly, with each connector being differentiated to engage only its corresponding signal contact. In addition, the design of connector assembly permits the antenna to be withdrawn through the connector assembly, at least partially, past the unused test signal contact. The antenna has at least two positions so that the profile of the antenna can be reduced for either storage, or for lower gain operation when the device is in a standby mode of operation.

Abstract: A method for fabricating a GeSi/Si/SiO.sub.2 heterostructure comprises the steps of: (a) providing a monocrystalline Si substrate; (b) defining a GeSi region within the Si substrate while leaving a Si cap overlying the GeSi region, the Si cap being an integral part of the monocrystalline substrate; and (c) oxidizing part of the Si cap to thereby produce the GeSi/Si/SiO.sub.2 heterostructure.

Abstract: A method is providing for a mobile station to vary the interval between scans by a mobile station for the beacon signals of cells in a communications system, in order to save battery power, when the mobile station is searching to select a serving cell. The method increases the interval between scans in response to the time elapsed since the start of the search. Initially, the scans are conducted with a small interval between the scans in the hope of quickly acquiring a serving cell. If a serving cell is not selected during this initial period of time, then the interval between scans is calculated to increase in response to the increase in elapsed time since the start of the search. If a serving cell is not selected during this period of calculated intervals, then the interval is set to a maximum limit to save battery power. A system for a mobile station to save power by varying the intervals between beacon signal scans when searching for a serving cell is also provided.

Abstract: A method is provided for applying chemical vapor deposition (CVD) copper (Cu) to integrated circuit substrates using a Cu(hfac)(ligand) precursor with a silylolefin ligand including combinations of C1-C8 alkyl groups with at least one C2-C8 alkyloxy group. The alkyloxy groups include, ethoxy, propoxy, butoxy, pentyloxy, hexyloxy, heptyloxy, octyloxy, and aryloxy, while the alkyl groups include methyl, ethyl, propyl, butyl, pentyl, hexyl, heptyl, octyl, and aryl. The oxygen atoms of the alkyloxy groups, and the long carbon chains of both the alkyl and alkyloxy groups, increase the stability of the precursor by contributing electrons to the Cu(hfac) complex. The improved bond helps insure that the ligand separates from the (hfac)Cu complex at consistent temperatures when Cu is to be deposited. Combinations of alkyloxy and alkyl groups allow the molecular weight of the precursor to be manipulated so that the volatility of the precursor is adjustable for specific process scenarios.

Abstract: A planarizing technique comprising: coating a topography overlying a substrate with a planarizing resist layer; softbaking the planarizing resist layer in the presence of a silicon-containing vapor or liquid; coating the planarizing resist layer with an imaging resist layer; softbaking the imaging resist; selectively exposing the imaging resist layer to light; developing the imaging resist layer; and etching the planarizing layer. The planarizing layer may comprise novolacs and other organic polymers used conventionally in lithographic processes. The planarizing layer may further comprise any organic acid moiety that is compatible with the solvent used to dissolve the resin. In particular, the acid moiety is indole-3-carboxylic acid. In another aspect, the invention comprises a silylated planarizing resist.

Abstract: A method is provided for forming multi-level profiles from a photoresist mask. The method includes exposing selected areas of a photoresist layer to two or more different patterns of light at different light dosage levels. For example, one pattern will be exposed to a relatively low dose of light, or to light for a short duration, and a second pattern will be exposed to a relatively high dose of light, or for a greater duration. The plurality of different exposures at different dosage levels occur prior to developing the photoresist. When the photoresist layer is developed, the pattern exposed to a lower dose of light will be etched substantially more slowly than the areas of the photoresist exposed to higher dose of light. By controlling the development process to completely remove the resist in the areas exposed to a high dose of light and only partially remove the resist in the areas exposed to a lower dose of light, a multi-level photoresist profile is formed.

Abstract: A method of blending water vapor with volatile Cu(hfac)TMVS (copper hexafluoroacetylacetonate trimethylvinylsilane) is provided which improves the deposition rate of Cu, without degrading the resistivity of the Cu deposited upon an integrated circuit surface. The method of the present invention uses a relatively small amount of water vapor, approximately 0.3 to 3% of the total pressure of the system in which chemical vapor deposition (CVD) Cu is applied. The method specifies the flow rates of the liquid precursor, carrier gas, and liquid water. The method also specifies the pressures of the vaporized precursor, vaporized precursor blend including carrier gas and water vapor. In addition, the temperatures of the vaporizers, chamber walls, and IC surfaces are disclosed. A Cu precursor blend is also provided comprising vaporized Cu(hfac)TMVS and water vapor. The ratio of water vapor pressure to vaporized precursor is approximately 0.5 to 5%.

Abstract: Methods and equipment for anisotropic, patterned conversion of copper into selectively removable compounds and for removal of the same are disclosed. In one embodiment a plasma reactor is used to anisotropically convert unmasked portions of a copper layer at low temperature into copper chloride. The copper chloride is removed by one or more of the following steps: (1) solvation by a solvent specific to the copper chloride; (2) vaporizing the copper chloride away; and (3) converting the copper chloride into a volatile, secondary compound. In another embodiment an ion implanter is used to anisotropically convert desired portions of a copper layer into copper oxide. The copper oxide is removed by one or more of the following steps: (1) solvation by a solvent specific to the copper oxide; (2) vaporizing the copper oxide away; and (3) converting the copper oxide into a volatile, secondary compound.

Abstract: A method of forming a semi-conductor structure forming, on a prepared substrate, a ferroelectric memory (FEM) gate unit. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on a FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer, and which is formed on a conductive channel precursor.The structure of the semiconductor includes a substrate, which may be either bulk silicon or SOI-type silicon, conductive channels of first and second type formed above the substrate, an FEM gate unit formed above a channel region, wherein the FEM gate unit includes a lower metal layer, an FE layer, and an upper metal layer, and wherein a conductive channel of a second type is formed under the FEM gate unit.

Abstract: A Ge--Si MOS transistor for high speed, high density applications in which a thin layer of silicon (Si) is doped to have a concentration of germanium (Ge) ions which is preferably between 10 and 30%. The germanium doped silicon is formed on a layer or substrate of insulator. Optional silicidation of the drain and source regions improves conductivity therein and the use of shallow SIMOX processing technologies results in a more cost-effective and rapid fabrication process.

Abstract: A system and method of information correction using the independently derived parity of a received (n,k) cyclic digital codeword as a means for error checking so that error bursts of up to ?(n-k)-.left brkt-top.log.sub.2 n.right brkt-top.! bit positions are corrected, where n is the number of bits in the codeword and k is the number of information bits in the codeword. The method incorporates prior art techniques of burst error correction using a generating polynomial and the generation of n syndromes, in which the bit positions of potential error bits in the received codeword are identified and replaced to generate potential replacement codewords for the received codeword. The method of correcting burst errors comprises the step of classifying replacement codewords with respect to their calculated parity. The method also comprises the step of using prior art error trapping techniques to supply a replacement codeword, as the corrected received codeword, when a single replacement codeword is generated.

Abstract: The present invention provides a system and method for using the brief time intervals between cellular telephone calls on a primary cellular network to transmit and receive data over a second data-only network. The invention uses the built-in capability of the primary network to monitor and track each call and to identify the relatively short-duration intervals between each call to pinpoint when a short burst of data from the second network can be transmitted without interfering with primary network calls. The data network includes a separate telephone exchange. Selected base stations of the primary cellular network are shared with the data-only network. Land lines or other connections link the data network exchange with the shared base stations. Preferably, the data network is accessible via a public packet data network. Data calls on the second network are directed to the shared base stations and inserted into the brief intervals between primary network calls.

Abstract: A battery power supply transposition circuit has been provided to control the use of batteries in a power source supplying multiple voltages from multiple batteries that share a least one common battery. The transposition circuit includes switches to provide selective interconnections between the battery terminals which allow the order of the series connected batteries to be changed. A battery interconnection controller is also included to control interconnections between batteries, and so allow alternate batteries to be used as the at least one common battery. Changing the selection of the at least one common battery provides a means for minimizing differences in the rate at which the batteries are depleted.

Abstract: A radio transceiver is provided for wireless communications, having an interface connection that is selectable between either an antenna or a cable interface. The radio transceiver is engaged to the antenna through an impedance matching network which translates the antenna impedance to match that of the radio transceiver. The radio transceiver can, alternately, be connected to external test equipment or performance enhancement equipment through the cable interface. Since the radio transceiver has the same impedance as most external test equipment, the antenna matching network is not required or used when test equipment is connected to the cable interface. In the present invention the cable interface at least partially disconnects the matching network whenever the cable interface is in use. Once the antenna has been disconnected, the impedance of the cable interface matches that of the radio transceiver.

Abstract: A multimode cache structure includes a predefined block of memory and controls for that block of memory which allow the memory block to perform multiple functions. The selectable, multiple functions include a cache mode, a SRAM mode, a flush mode and an invalidate mode. A control register is defined and is associated with the predefined memory block, which control register includes multiple status bits therein. Each of the status bits corresponds to one of the multiple functions and, when a particular status bit is set, the predefined block of memory performs a function corresponding to the status bit that is set.

Abstract: A voltage gradient measurement device is provided for determining the remaining lifetime of a battery used to power a radio, pager, cellular telephone, or similar device. The battery is attached to a first circuit element to obtain a history of the battery voltage which is used to determine the differential battery voltage. The battery is also attached to a second circuit element which measures the voltage margin between the battery voltage and a reference voltage representing the battery end-of-life condition. A third circuit element divides the voltage margin output of the second circuit element by the differential battery voltage output of the first circuit element to estimate the time that will elapse until the battery voltage approximately equals the reference end-of-life voltage level.