Abstract: Sub-micron features are defined photo-lithographically by combining phase-shifting techniques with conventional photo lithographic techniques. In a first step, phase-shifting edges are defined in a photoresist layer. Dark-bands develop at the phase-shifting edges due to wavefront interference of an illuminating radiation in a subsequent exposure step. Development leaves behind sub-micron sections of photoresist which were covered by the dark-band regions. The dark-band sections are hardened and overcoated with a new layer of photoresist. A second pattern is projected onto the second layer of photoresist using conventional techniques. The second pattern is developed so as to create features having dimensions reduced by parts of the dark-band sections previously developed.

Abstract: A graduated concentration profile is used defining a buried isolation region in a semiconductor device. Smaller concentrations of dielectric-defining particles are used for implantation at the deepest levels of the isolation region in order to reduce the defect density in an overlying epi layer.

Abstract: The invention provides a trilayer structure and photolithographic method which permits use of high-resolution optics with a relatively small depth of focus for patterning a substrate. A trilayer lithographic structure in accordance with the invention comprises: (a) an out-gas resistant planarization layer deposited on a substrate; (b) a chemical-vapor-deposited interfacial film formed on the planarization layer; and (c) a photosensitive resist layer of a thickness equal to or less than one micron deposited on the interfacial film. A method in accordance with the invention comprises the steps of: (a) depositing an out-gas resistant planarization layer on a substrate; (b) chemical-vapor-depositing an interfacial film on the planarization layer; and (c) forming a photosensitive resist layer of a thickness equal to or less than one micron on the interfacial film.

Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.

Abstract: Crowbar current in a CMOS amplifier circuit is limited during a transition state where one transistor is being turned on and another transistor is being turned off. The transistor that is being turned off is caused to pass through a midpoint state before the transistor that is being turned on is allowed to transition through a similar midpoint state. In one embodiment, independent gate voltages are applied to the P and N transistors of a CMOS amplifier. The gate voltages are independently controlled prior to passage through a midpoint level and then converge towards one another after passage through the midpoint state.

Abstract: Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

Abstract: An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memory cells are accessed for read or write operations in another array. Also, all the cells in a row of the other array may be precharged as the memory cells in the one array are accessed independently for read or write operations. Accesses to memory cells in addressed rows alternate from one array to another so that the signal conditioning of the memory cells in one array can take place before access in needed and while memory cells are being accessed in another array. Improved status logic unambigously designates the conditions of empty, half full and full, independent of the sequence of data read and write operations.