Abstract: A system and method is provided for use in register-based CPUs for processing data in the CPU register bank while concurrently loading and unloading data into additional register banks. The additional register banks are then sequentially connected to the CPU datapath for data processing. Interconnections between the various register banks in the CPU and appropriate data buses for performing the load/process/unload functions are controlled by a load/store control logic block which can be a simple state machine processor. The load/store control logic is triggered by a software instruction encountered at the end of particular computational routines during normal program execution. This software instruction replaces the need for separate load and store instructions and their attendant clock cycles. The invention substantially decreases unused data processor time since the arithmetic and logic unit (ALU) can be sequentially connected to register banks which have been pre-loaded with data for processing.

Abstract: The invention provides a technique for forming a MOS transistor with reduced leakage current and a shorter channel length between source and drain electrodes. The transistor includes a gate electrode between raised source and drain electrodes that are formed from epitaxial silicon. Typically, the raised source and drain electrodes are thin where the intersect the gate electrode so that epitaxial notches are formed between the gate sidewall insulation and the source/drain electrodes. To protect the source/drain junction areas underlying the epitaxial notches from undesired penetration of doping impurities used in the fabrication of the electrodes, the notches are covered with insulation material. In a special process step, performed between forming the epitaxial layers and implanting the layers with dopants to form source and drain electrodes, insulation material is added to the initial, relatively thin, gate sidewalls that insulate the gate electrode from the source/drain electrodes.

Abstract: A control circuit which regulates an ac power output device. The control circuit is operatively connected to the ac power output and measures the ac signal with a diode to generate a control signal stimulus. A second diode is operatively connected to the power measuring diode so that the two diodes have the same voltage drops associated with the quiescent operation of the diodes. Quiescent voltage changes in the power measuring diode are canceled by the matching quiescent voltage change in the second diode. In this manner, power measurement errors associated with diode quiescent voltage changes are minimized.

Abstract: The invention provides an improved technique for forming a MOS transistor having lightly doped source and drain junction regions and low parasitic capacitance. The transistor includes raised source and drain electrodes which are strapped to the substrate adjacent the gate insulation. The raised electrodes include interconnect portions which overlie the field oxide separating the semiconductor substrate into a plurality of active regions. The source and drain electrodes are thickest where each overlies its junction with the substrate in order to control the depth of penetration of doping impurities into the substrate. After doping the electrodes, a rapid thermal anneal is performed which diffuses the doping impurities throughout the electrodes and into thin junction regions of the substrate, immediately beneath the source and drain electrodes.

Abstract: The present invention involves a receiving method and apparatus for use in a communication system wherein a spread-spectrum signal containing information bits is transmitted within an environment tending to produce multipath fading. The receiving apparatus includes a channel estimator which estimates channel coefficients, preferably corresponding to the level of correlation between the various multipath components of the spread-spectrum signal and a cell-correlation signal. A channel selector is configured to select one or more of the multipath components based on the channel coefficients, typically choosing multipath components with the greatest level of correlation, a condition which is indicative of a high signal-to-noise power ratio.

Abstract: The invention provides a method and structure in which a nucleating species [54] is implanted through apertures [52] of a metal-phobic layer [40] into a support layer [17] and copper or a like metal is selectively grown at the implant site or sites. The implant support layer [17] is preferably composed of a material which inhibits diffusion therethrough of the copper or other like grown metal.

Abstract: Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the Latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

Abstract: A modified lead frame is provided for use with electrical component test handlers. A conventional multiple-parallel-conductor lead frame is modified to include two broad, electrically conductive shields positioned on opposite sides of the lead frame. Each shield covers a major portion of one side of the lead frame. Such lead frames are designed for mounting in a predetermined orientation on a lead frame holder, with one side facing toward, and the other side facing away from, the major mass of the holder. The conductive shield positioned on the side facing away from the holder on the modified lead frame of the present invention is electrically coupled to one or more selected conductors on the lead frame. The one or more selected conductors include the power or ground conductor which supplies power to a test component during tests. The shield which faces toward the holder is electrically isolated from all the conductors on the lead frame by an intermediate insulating layer.

Abstract: The invention provides an improved planarizing methodology for forming high-definition photolithographic masks of the type used in semiconductor integrated circuit manufacturing. A layer of planarizing photoresist is first applied to the surface topography of a semiconductor wafer substrate and shallow-penetrating radiation is then used to irradiate the surface of the photoresist. The radiation creates a blanket irradiated layer, adjacent the surface of the resist, consisting of an acid and resist in solution. The acid/resist solution readily absorbs and incorporates silicon. Next, the wafer is exposed to a silicon-containing compound, or softbaked in a silicon-containing environment, creating a silicon-enriched region adjacent the surface of the photoresist. An imaging resist is then applied to the resist, and a photolithographic mask is formed in the imaging resist. An etching step transfers the mask to the silicon-enriched region of the photoresist.

Abstract: A pager decoding system is provided which is compatible with the POCSAG encoding standard and which improves battery savings. The disclosed pager includes a baud rate detector for evaluating incoming transmissions to determined if the baud rate is compatible with the decoder, and a preamble detector for determining if preamble code is being transmitted. Baud rate information and preamble code information are sampled frequently when the pager's radio receiver is tuned on, to evaluate whether a valid transmission is being received and whether the pager's internal clock is synchronized with the transmission. In the methodology of the invention, when the pager is on standby and waiting to receive a transmission the radio receiver is periodically energized to search for valid data having the correct baud rate, and to search for POCSAG preamble code. Signals with the incorrect baud rate are quickly detected and the radio circuit is shut off to save battery power.

Abstract: A graduated concentration profile is used for defining a buried isolation region in a semiconductor device. Smaller concentrations of dielectric-defining particles are used for implantation at the deepest levels of the isolation region in order to reduce the defect density in an overlying epi layer.

Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A digit reversing system is disclosed for handling mixed radix FFT operations with arbitrary arrangements of radices. In a first step, all bits in an integer field of size log.sub.2 N are position reversed. In a second step, subfields of the output produced in the first step are individually unreversed at the local level to produce unreversed digits. The output is used for appropriately arranging input terms applied to a mixed-radix multi-stage Fast Fourier Transform (FFT) process.

Abstract: A method is provided for improving the electrical isolation between surface regions and underlying support regions in SIMOX buried oxide wafers. The method implants nitrogen ions into a wafer to approximately the same depth as oxygen ions are implanted during SIMOX processing. A subsequent heating step causes the nitrogen ions to migrate to the interface region between the buried oxide and the upper and lower semiconductor regions of the substrate. The nitrogen passivates the interface regions to reduce the presence of buried free electrons trapped in the substrate. Nitrogen implantation can be performed before, during, or after the oxygen is implanted. Nitrogen ions can also be implanted after the SIMOX buried silicon dioxide layer has been formed. If the latter alternative is followed, the wafer must be subsequently heated to migrate the nitrogen ions to the interface regions within the substrate. Such subsequent heating can be performed as part of the formation of devices on the substrate.

Abstract: A one-chip address generator for producing a sequence of address signals for application to a memory containing a plurality of circular buffers. The address generator chip is capable of processing service requests from a plurality of channels on a prioritized basis. Service requests can arrive asynchronously at different rates. A channel-specific length or overlap value can be assigned to each servicing of a request. A seamless pipeline structure is provided for processing the service requests of subsequent channels immediately after completion of service for a first requesting channel.

Abstract: A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.

Abstract: The invention provides a method of forming shallow SIMOX (Separation by IMplantation of OXygen) substrates by implantation of molecular oxygen ions (O.sub.2 +), instead of implanting atomic oxygen ions (O+) as is done in prior art SIMOX processes. Use of molecular oxygen ions (O.sub.2 +) doubles the yield of oxygen atoms implanted for each unit of electric charge deposited in the wafer. The resultant structure, after annealing, has a defect density which is not substantially different from SIMOX processing using atomic oxygen ions (O+). An alternative method for implanting molecular nitrogen ions is also disclosed.

Abstract: A method for forming interconnects in an integrated circuit chip which includes a plurality of active devices over which a layer of dielectric material is deposited. The method comprises: (a) depositing a selective nucleating layer on the dielectric layer; (b) depositing a sacrificial layer over the nucleating layer; (c) pattering the sacrificial layer and nucleating layer such that the resulting pattern of the nucleating layer and sacrificial layer is equivalent to the desired pattern of conductive lines; (d) depositing a sidewall guide material over the patterned sacrificial and nucleating layers; (e) forming sidewall guides; (f) removing the sacrificial layer; and (g) depositing conductive material between the sidewall guides and on the nucleating layer. The nucleating layer may comprise titanium nitride, the sacrificial layer may comprise silicon dioxide, the sidewall guide material may comprise silicon nitride, and the conductive material may comprise copper.

Abstract: A BiCMOS structure in which the bipolar transistor is preferably arranged vertically and the MOS transistors are formed on insulator. SIMOX techniques may be used to form a starting substrate.