Patents Assigned to Shin-Etsu Handotai Co., Ltd.
  • Publication number: 20230235481
    Abstract: A silicon single crystal substrate for vapor phase growth, having the silicon single crystal substrate being made of an FZ crystal having a resistivity of 1000 ?cm or more, wherein the surface of the silicon single crystal substrate is provided with a high nitrogen concentration layer having a nitrogen concentration higher than that of other regions and a nitrogen concentration of 5×1015 atoms/cm3 or more and a thickness of 10 to 100 ?m.
    Type: Application
    Filed: March 23, 2021
    Publication date: July 27, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Keitaro TSUCHIYA, Masaru SHINOMIYA, Weifeng QU
  • Publication number: 20230230926
    Abstract: A method for producing a semiconductor apparatus capable of producing a semiconductor apparatus with improved transmission loss characteristic using an interposer substrate in which semiconductor devices formed on a silicon single crystal substrate are connected to each other by a through electrode, the method including: a step of providing the silicon single crystal substrate containing a dopant; a step of forming the semiconductor devices and the through electrode on the silicon single crystal substrate to obtain the interposer substrate; and a step of irradiating a particle beam to at least around a formation part for the through electrode on the silicon single crystal substrate to deactivate the dopant in a region around the formation part for the through electrode.
    Type: Application
    Filed: May 26, 2021
    Publication date: July 20, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi OHTSUKI, Hiroshi TAKENO
  • Patent number: 11705330
    Abstract: A substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has a plurality of silicon single crystal substrates that are joined and has a thickness of more than 2000 ?m, and the plurality of silicon single crystal substrates are produced by a CZ method and have a resistivity of 0.1 ?cm or lower. This provides: a substrate for an electronic device having a nitride semiconductor film formed on a silicon substrate, where the substrate for an electronic device can suppress a warp and can also be used for a product with a high breakdown voltage; and a method for producing the same.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 18, 2023
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazunori Hagimoto, Shouzaburo Goto
  • Publication number: 20230212782
    Abstract: A method for manufacturing a silicon single-crystal substrate having a carbon diffusion layer on a surface, proximity gettering ability, and high strength near the surface, and hardly generating dislocation or extending dislocation, includes: a step of adhering carbon on a surface of a silicon single-crystal substrate by an RTA treatment of the silicon single-crystal substrate in a carbon-containing gas atmosphere; a step of forming a 3C-SiC single-crystal film on the surface of the silicon single-crystal substrate by reacting the carbon and the silicon single-crystal substrate; a step of oxidizing the 3C-SiC single-crystal film to be an oxide film and diffusing carbon inward the silicon single-crystal substrate by an RTA treatment of the silicon single-crystal substrate on which the 3C-SiC single-crystal film is formed, the RTA treatment being performed in an oxidative atmosphere; and a step of removing the oxide film.
    Type: Application
    Filed: July 23, 2021
    Publication date: July 6, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Weifeng QU, Shizuo IGAWA, Ken SUNAKAWA
  • Publication number: 20230215817
    Abstract: A bonded semiconductor light-receiving device including an epitaxial layer to serve as a device-functional layer, and a support substrate made of a material different from that of the device-functional layer and bonded to the epitaxial layer via a bonding material layer. The device-functional layer has a bonding surface with an uneven pattern formed thereon.
    Type: Application
    Filed: June 8, 2021
    Publication date: July 6, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Junya ISHIZAKI
  • Publication number: 20230215976
    Abstract: A bonded semiconductor device including an epitaxial layer, and a support substrate made of a material different from that of the epitaxial layer and bonded to the epitaxial layer. Any one of the epitaxial layer and the support substrate has a bonding surface with a radial pattern including recesses or protrusions radially spreading from a certain point on the bonding surface as a center.
    Type: Application
    Filed: June 8, 2021
    Publication date: July 6, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Junya ISHIZAKI
  • Publication number: 20230207399
    Abstract: A method for dry-etching a semiconductor substrate having an oxide film, including: evaluating a film quality of the oxide film and determining a time for performing the dry-etching on a basis of results of the evaluation in advance. This provides a method for controlling the etching amount of an oxide film accurately and suppressing over-etching and insufficient etching without influence from variation in the film quality of the oxide film when dry-etching the oxide film on the surface of the semiconductor substrate.
    Type: Application
    Filed: March 3, 2021
    Publication date: June 29, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi OHTSUKI, Tatsuo ABE
  • Publication number: 20230197533
    Abstract: A method for evaluating a peripheral strain of a wafer having a polycrystalline film formed on a surface, the method including: using, as the wafer having the polycrystalline film formed on the surface, a wafer of a silicon single crystal substrate having a polycrystalline film formed on a surface; performing a pre-treatment of removing a surface of the polycrystalline film; subsequently allowing an infrared laser to enter a periphery of the wafer from a back surface; and evaluating the peripheral strain of the wafer from a polarization degree of the infrared laser transmitted through the wafer.
    Type: Application
    Filed: June 1, 2020
    Publication date: June 22, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Yushi ANDO
  • Publication number: 20230175166
    Abstract: The present invention is a single-crystal pulling apparatus including: a pulling furnace which has a heater and a crucible arranged and which has a central axis; and a magnetic field generation device having superconducting coils, where the magnetic field generation device has four of the superconducting coils, two of the superconducting coils are arranged in each of two regions divided by a cross section that includes an X axis, the X axis being a direction of lines of magnetic force at the central axis in the horizontal plane including all the coil axes of the four superconducting coils, and includes the central axis of the pulling furnace so as to have line symmetry about the cross section, the four superconducting coils are all arranged so that the coil axes have an angle within a range of more than ?30° and less than 30° relative to a Y axis, the direction of the lines of magnetic force thereof have line symmetry about the cross section, and in each of the regions, the two superconducting coils generate
    Type: Application
    Filed: March 19, 2020
    Publication date: June 8, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kiyotaka TAKANO, Wataru YAJIMA, Kosei SUGAWARA, Hiroyuki KAMADA, Tomohiko OHTA
  • Publication number: 20230178390
    Abstract: A method for etching a silicon wafer, the method including a spin etching step in which while an acid etching solution is supplied to a front or back side surface of a silicon wafer through a supply nozzle, the silicon wafer is rotated to expand a supply range of the acid etching solution to perform acid etching throughout the front or back side surface of the silicon wafer. Before the rotation of the silicon wafer is started, an acid mixture containing at least hydrofluoric acid and nitric acid is added dropwise within an impinging jet area which is located immediately below the supply nozzle, and in which the acid etching solution supplied through the supply nozzle impinges on the surface of the silicon wafer. After the impinging jet area is covered with the acid mixture, the rotation of the silicon wafer is started to perform the spin etching step.
    Type: Application
    Filed: March 2, 2021
    Publication date: June 8, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kuniaki OONISHI
  • Publication number: 20230173633
    Abstract: A manufacturing method for a substrate wafer, including: a wafer having a first and second main surface; forming a flattening resin layer on second main surface; with the flattening resin layer adsorbed and held as a reference surface, grinding or polishing first main surface as a first processing; removing flattening resin layer from the wafer; with the wafer's first main surface subjected to the first processing adsorbed and held, grinding or polishing second main surface as a second processing; with the second main surface subjected to second processing adsorbed and held, further grinding or polishing first main surface as a third processing; with first main surface subjected to third processing adsorbed and held, further grinding or polishing second main surface as a fourth processing to obtain a substrate wafer, wherein first processing and/or third processing is executed such that the wafer has a central concave or central convex thickness distribution.
    Type: Application
    Filed: March 17, 2021
    Publication date: June 8, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryo TAGA, Yuki TANAKA
  • Publication number: 20230170208
    Abstract: A method for forming a thermal oxide film on a semiconductor substrate, including: a correlation acquisition step of providing a plurality of semiconductor substrates; a substrate cleaning step of cleaning a semiconductor substrate; a thermal oxide film thickness estimation step of determining a constitution of a chemical oxide film formed on the semiconductor substrate by the cleaning in the substrate cleaning step and, based on the correlation, estimating a thickness of a thermal oxide film on a hypothesis that the semiconductor substrate has been subjected to a thermal oxidization treatment conditions in the correlation acquisition step; a thermal oxidization treatment condition determination step of determining thermal oxidization treatment conditions based on the thermal oxidization treatment conditions in the correlation acquisition step so that the thermal oxide film is a predetermined thickness; and a thermal oxide film formation step of forming a thermal oxide film on the semiconductor substrate.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 1, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi OHTSUKI, Tatsuo ABE
  • Publication number: 20230154748
    Abstract: A method for manufacturing a semiconductor substrate by forming an insulator film and a semiconductor single crystal layer on a surface of a silicon single crystal substrate to manufacture a semiconductor substrate having the semiconductor single crystal layer on the insulator film, the method including at least the steps of: forming a silicon nitride film having an epitaxial relationship with the silicon single crystal substrate on the surface of the silicon single crystal substrate as the insulator film by subjecting the silicon single crystal substrate to a heat treatment under a nitrogen gas-containing atmosphere; and forming the semiconductor single crystal layer on the silicon nitride film by epitaxial growth. This makes it possible to obtain a semiconductor substrate by simple method with high productivity at low cost even when the insulator film provided between the silicon single crystal substrate and the semiconductor single crystal layer is a silicon nitride film.
    Type: Application
    Filed: October 8, 2020
    Publication date: May 18, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Miho NIITANI, Taishi WAKABAYASHI, Kento YAMADA, Kazuhiko YOSHIDA
  • Publication number: 20230154761
    Abstract: A method for manufacturing an SOI wafer including a step of performing an adjustment to a film thickness of an SOI layer of the SOI wafer by wet etching. In the step of performing the adjustment to the film thickness of the SOI layer, a first etching step of etching a surface of the SOI layer using an SC1 solution; and a second etching step of etching the surface of the SOI layer by bringing the SOI layer into contact with ozone water to form an oxide film on the surface of the SOI layer and then bringing the formed oxide film into contact with an HF-containing aqueous solution to remove the oxide film, are performed in combination. The etchings are performed such that a removal amount of the SOI layer in the first etching step is smaller than that in the second etching step.
    Type: Application
    Filed: April 14, 2021
    Publication date: May 18, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji AGA, Isao YOKOKAWA
  • Publication number: 20230154742
    Abstract: A method for cleaning a semiconductor wafer to clean a semiconductor wafer after polishing, including: performing a first ozone-water treatment step of cleaning the polished semiconductor wafer with ozone water to form an oxide film; performing a brush cleaning step of brush-cleaning the semiconductor wafer with carbonated water after the first ozone-water treatment step; and then performing a second ozone-water treatment step including cleaning the semiconductor wafer with hydrofluoric acid to remove the oxide film, followed by cleaning with ozone water to form an oxide film again. This second ozone-water treatment step is performed one or more times. The method for cleaning a semiconductor wafer achieves cleaning level equivalent to that with SC1, reduces or prevents defect generation on a wafer surface and surface roughness degradation which would otherwise occur when SC1 is used, and also results in cost reduction and environmental load reduction.
    Type: Application
    Filed: February 18, 2021
    Publication date: May 18, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kensaku IGARASHI
  • Publication number: 20230138632
    Abstract: A single-crystal pulling apparatus including: a pulling furnace having a central axis; and a magnetic field generation device arranged around the pulling furnace and having superconducting coils, the apparatus applying a horizontal magnetic field to the molten semiconductor raw material, two coil axes in the two pairs of the superconducting coils are included in a single horizontal plane, and when a direction of lines of magnetic force at the central axis of the pulling furnace in the horizontal plane is determined as an X axis, a center angle ? having the X axis between the two coil axes is 100 degrees or more and 120 degrees or less. This makes it possible to reduce the height of the coils, to raise the magnetic field center close to the melt surface of the semiconductor raw material, and to obtain a single crystal having a lower oxygen concentration than conventional single crystals.
    Type: Application
    Filed: February 22, 2021
    Publication date: May 4, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kiyotaka TAKANO, Kosei SUGAWARA, Hiroyuki KAMADA, Takahide ONAI, Tomohiko OHTA
  • Publication number: 20230137813
    Abstract: A method for polishing a wafer in order to correct a shape of a polished wafer subjected to polishing, by pressing the wafer to a polishing pad while continuously supplying a composition for polishing containing water to perform correction-polishing, the method including the steps of: measuring the shape of the polished wafer before performing the correction-polishing; determining, in accordance with the measured shape of the polished wafer, a kind and concentration of a surfactant to be contained in the composition for polishing; and performing the correction-polishing while supplying the composition for polishing adjusted on a basis of the determined kind and concentration of the surfactant. This provides a method and apparatus for polishing a wafer that make it possible to reduce, in the latter polishing step, a variation in the shape of the wafer that occurred in a preceding polishing step.
    Type: Application
    Filed: February 8, 2021
    Publication date: May 4, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Masaaki OSEKI, Tatsuo ABE, Michito SATO
  • Publication number: 20230125000
    Abstract: A method for measuring a DIC defect shape on a silicon wafer, the method including steps of: detecting a DIC defect on a main surface of the silicon wafer with a particle counter; specifying position coordinates of the detected DIC defect; and measuring a shape including at least a height or depth of the detected DIC defect by utilizing the specified position coordinates according to phase-shifting interferometry. The method for measuring a DIC defect shape by which the shape including size of DIC defect generated on a main surface of a silicon wafer is easily and precisely measured.
    Type: Application
    Filed: March 31, 2021
    Publication date: April 20, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kazuya TOMII
  • Patent number: 11584037
    Abstract: A wire saw apparatus including: a plurality of wire guides; a wire row formed of a wire which is wound around the plurality of wire guides and configured to reciprocatively travel in an axial direction; a nozzle configured to supply a coolant or slurry to the wire; a workpiece-holding portion configured to suspend and hold a workpiece plate having a workpiece bonded thereto with a beam interposed therebetween; a workpiece-feeding mechanism configured to press the workpiece against the wire row; and a mechanism configured to adjust a parallelism of axes of the plurality of wire guides around which the wire row is formed. Thereby, a wire saw apparatus and a method for manufacturing a wafer are provided which enable manufacturing of a wafer having any warp shape by controlling a warp in a wire travelling direction of a sliced workpiece.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: February 21, 2023
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazutoshi Mizushima, Toshiaki Otaka, Tatsuo Enomoto, Yuichi Shimizu
  • Publication number: 20230047427
    Abstract: A method for producing a silicon single crystal, wherein a silicon nitride powder is introduced into a raw material before start of melting and the silicon single crystal doped with nitrogen is pulled by Czochralski method, wherein nitrogen doping is performed while an upper limit amount of usable silicon nitride powder is limited based on an amount of carbon impurities contained in the silicon nitride powder so that a carbon concentration in the silicon single crystal is equal to or less than allowable value. This makes it possible to achieve the required nitrogen doping amount at low cost while achieving the low carbon-concentration specification.
    Type: Application
    Filed: December 1, 2020
    Publication date: February 16, 2023
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kosei SUGAWARA, Ryoji HOSHI, Tomohiko OHTA