Patents Assigned to Shin-Etsu Handotai Co., Ltd.
  • Publication number: 20220136130
    Abstract: An apparatus for manufacturing a single crystal according to a Czochralski method, including: a main chamber housing crucibles for a raw-material melt and heater for heating the raw-material melt; a pulling chamber at an upper portion of the main chamber and a single crystal pulled from the raw-material melt; a cooling cylinder extending from a ceiling portion of the main chamber toward a surface of the raw-material melt to surround the single crystal; an auxiliary cooling cylinder inside the cooling cylinder; and a diameter-enlargement member to fit into the auxiliary cooling cylinder. The auxiliary cooling cylinder has a slit penetrating in an axial direction to come into close contact with the cooling cylinder by pushing the diameter-enlargement member into the auxiliary cooling cylinder to enlarge the diameter of the auxiliary cooling cylinder. This enables efficient cooling of a growing single crystal and increases the growth rate of the single crystal.
    Type: Application
    Filed: December 26, 2019
    Publication date: May 5, 2022
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Takumi KOBAYASHI, Kazuya YANASE, Atsushi OKAI, Susumu SONOKAWA, Atsushi IWASAKI
  • Patent number: 11305994
    Abstract: A method is provided for refining an argon gas, in which oxygen is added to the argon gas containing hydrogen, carbon monoxide (CO), and oxygen as impurities so that the hydrogen and the CO are converted into water and carbon dioxide in a catalyst tower, or hydrogen is added to the argon gas so that the oxygen is converted into the water; the method including: monitoring the hydrogen, the CO, and the oxygen on an outlet side of the catalyst tower; and at least one of adding the oxygen to the argon gas when any one of the hydrogen and the CO is detected on the outlet side of the catalyst tower, and adding the hydrogen when the oxygen is detected, wherein the oxygen or the hydrogen to be added is intermittently added to the catalyst tower relative to continuous supply of the argon gas to the catalyst tower.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: April 19, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yasushi Kurosawa, Hideaki Matsushima
  • Patent number: 11298796
    Abstract: A method for double-side polishing a wafer uses a double-side polishing machine wherein a carrier which is yet to be arranged in the double-side polishing machine is previously subjected to two-stage double-side polishing which uses a double-side polishing machine different from the double-side polishing machine adopted for double-side polishing the wafer and includes primary polishing using slurry containing abrasive grains and secondary polishing using an inorganic alkali solution containing no abrasive grain, the carrier subjected to the two-stage double-side polishing is arranged in the double-side polishing machine adopted for double-side polishing the wafer, and the double-side polishing of the wafer is performed. Consequently, the method for double-side polishing a wafer enables suppressing damages to wafers to be polished immediately after arranging the carrier between the upper and lower turntables.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 12, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yuki Tanaka, Daichi Kitazume, Syuichi Kobayashi
  • Publication number: 20220059343
    Abstract: A method for cleaning a semiconductor silicon wafer including: an ozone water treatment step after polishing in ozone water, a step of performing a first ultrasonic-wave-ozone-water treatment of cleaning at room temperature while immersing in ozone water and applying ultrasonic waves; and a step of performing a second ultrasonic-wave-ozone-water treatment of, after the step of performing the first ultrasonic-wave-ozone-water treatment, pulling out the semiconductor silicon wafer from the ozone water, performing rotation process, and cleaning at room temperature while immersing in ozone water and applying ultrasonic waves; wherein the step of performing the second ultrasonic-wave-ozone-water treatment is performed, and a hydrofluoric acid treatment step and an ozone water treatment step are performed.
    Type: Application
    Filed: September 17, 2019
    Publication date: February 24, 2022
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kensaku IGARASHI
  • Patent number: 11248306
    Abstract: An anodic-oxidation equipment for forming a porous layer on a substrate to be treated, including: an electrolytic bath filled with an electrolytic solution; an anode and a cathode disposed in the electrolytic solution; and a power supply for applying current between the anode and the cathode in the electrolytic solution, wherein the anode is the substrate to be treated, and the cathode is a silicon substrate having a surface on which a nitride film is formed. This provides a cathode material in anodic-oxidation for forming porous silicon by an electrochemical reaction in an HF solution, the cathode material having a resistance to electrochemical reaction in an HF solution and no metallic contamination, etc., and furthermore, being less expensive than a conventional cathode material. Furthermore, high-quality porous silicon is provided at a lower cost than has been conventional.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 15, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Masaro Tamatsuka
  • Patent number: 11244852
    Abstract: The present invention is a method for manufacturing a bonded SOI wafer, including: preparing, as a base wafer, a silicon single crystal wafer whose initial interstitial oxygen concentration is 15 ppma or more ('79ASTM); forming a silicon oxide film on a surface of the base wafer by heating the base wafer in an oxidizing atmosphere such that a feeding temperature at which the base wafer is fed into a heat treatment furnace for the heat treatment is 800° C. or more, and the base wafer is heated at the feeding temperature or higher; bonding the base wafer to the bond wafer with the silicon oxide film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a method for manufacturing a bonded SOI wafer by a base oxidation method which suppresses the formation of oxide precipitates in a base wafer while suppressing slip dislocation.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: February 8, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Ishizuka, Setsuya Hama
  • Patent number: 11244851
    Abstract: A method for manufacturing an SOI wafer by performing a sacrificial oxidation treatment and reducing a thickness of an SOI layer of the SOI wafer, in which: the SOI wafer on which the sacrificial oxidation treatment is performed has a film thickness distribution with a one-way sloping shape; a thermal oxidation in the sacrificial oxidation treatment is performed by combining a non-rotating oxidation and a rotating oxidation, using a vertical heat treatment furnace; whereby a thermal oxide film having an oxide film thickness distribution with a one-way sloping shape canceling the film thickness distribution with a one-way sloping shape of the SOI layer, is formed on a surface of the SOI layer; and by removing the formed thermal oxide film, an SOI wafer having an SOI layer whose film thickness distribution with a one-way sloping shape has been resolved is manufactured.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 8, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Hiroji Aga
  • Publication number: 20220016802
    Abstract: A method for slicing a workpiece includes feeding and slicing a workpiece held by a workpiece holder with a bonding member therebetween, while reciprocatively traveling a fixed abrasive grain wire wound around multiple grooved rollers to form a wire row, so that the workpiece is sliced at multiple positions simultaneously. The bonding member has a grindstone part. The method includes, after the workpiece is sliced and before it is drawn out from the wire row, a fixed-abrasive-grain removal step of pressing the wire against the grindstone to remove fixed abrasive grains from the wire while reciprocatively traveling. In the fixed-abrasive-grain removal step, the wire rate is 100 m/min. or less, and the load on each line of the wire is 30 g or more. The method prevents a sliced workpiece from catching a wire and from causing saw mark and wire break in drawing out the wire after slicing.
    Type: Application
    Filed: December 25, 2019
    Publication date: January 20, 2022
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kenji KOBAYASHI
  • Patent number: 11225729
    Abstract: A method for manufacturing a SiC single crystal reducing crystallinity degradation at a wafer central portion wherein a growth container surrounds a heat-insulating material with a top temperature measurement hole, a seed crystal substrate at an upper portion inside the container, and a silicon carbide raw material at a lower portion of the container and sublimated to grow a SiC single crystal on the seed crystal substrate. A center position hole deviates from a center position of the seed crystal substrate and moves to the periphery side of the center of the seed crystal substrate. A SiC single crystal substrate surface is tilted by a {0001} plane and used as the seed crystal substrate. The SiC single crystal grows with the seed crystal substrate directed to a normal vector of the seed crystal substrate basal plane parallel to the main surface and identical to the hole in a cross-sectional view.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: January 18, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toru Takahashi, Hitoshi Ikeda, Yuichi Matsumoto, Tetsuro Aoyama
  • Patent number: 11222780
    Abstract: A method for evaluating a silicon wafer, including: a pre surface defect measuring step for performing a surface defect measurement on the silicon wafer in advance, a cleaning step of alternately repeating on the silicon wafer an oxidation treatment by ozone water and an oxide film removal treatment by hydrofluoric acid under a condition of not completely removing an oxide film formed on a surface of the silicon wafer, and an incremental defect measuring step of performing a surface defect measurement on the silicon wafer after the cleaning step and measuring incremental defects that increased relative to defects measured in the pre surface defect measuring step, wherein the cleaning step and the incremental defect measuring step are alternately performed repeatedly multiple times and the silicon wafer is evaluated based on a measurement result of the incremental defects after each cleaning step.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: January 11, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kensaku Igarashi, Tatsuo Abe
  • Patent number: 11205599
    Abstract: An evaluation method of a silicon epitaxial wafer, including using a photoluminescence (PL) measuring apparatus to measure a PL spectrum of the mirror wafer and adjusting the apparatus so emission intensity of a TO-line becomes 30000 to 50000 counts, irradiating the silicon epitaxial wafer with an electron beam, measuring PL spectrum from an electron beam irradiation region, and sorting out and accepting a silicon epitaxial wafer which has emission intensity resulting from a CiCs defect of the PL spectrum being 0.83% or less of the emission intensity of the TO-line and from a CiOi defect being 6.5% or less of the emission intensity of the TO-line.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: December 21, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Yasushi Mizusawa
  • Patent number: 11189475
    Abstract: A desolvation unit performs desolvation by heating after a sample solution is turned to sample mist by a nebulizer. A sample gas that contains the desolvated sample mist and a carrier gas is introduced through a sample introduction tube to a plasma torch. An addition unit for adding, to the sample introduction tube, a water-containing gas is provided. The addition unit includes a container that contains ultrapure water, a gas tube for introducing the carrier gas into the ultrapure water to cause bubbling, and a gas tube for adding the water-containing gas, to the sample introduction tube. The plasma torch generates an inductively coupled plasma under the condition that supplied power is set to a range of 550 W to 700 W. Generation of interfering molecule ions due to an element having a high ionization potential is inhibited when an element in a sample ionized by the plasma is analyzed.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 30, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kenji Araki
  • Publication number: 20210362373
    Abstract: A wire saw apparatus including: a plurality of wire guides; a wire row formed of a wire which is wound around the plurality of wire guides and configured to reciprocatively travel in an axial direction; a nozzle configured to supply a coolant or slurry to the wire; a workpiece-holding portion configured to suspend and hold a workpiece plate having a workpiece bonded thereto with a beam interposed therebetween; a workpiece-feeding mechanism configured to press the workpiece against the wire row; and a mechanism configured to adjust a parallelism of axes of the plurality of wire guides around which the wire row is formed. Thereby, a wire saw apparatus and a method for manufacturing a wafer are provided which enable manufacturing of a wafer having any warp shape by controlling a warp in a wire travelling direction of a sliced workpiece.
    Type: Application
    Filed: November 1, 2018
    Publication date: November 25, 2021
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kazutoshi MIZUSHIMA, Toshiaki OTAKA, Tatsuo ENOMOTO, Yuichi SHIMIZU
  • Publication number: 20210358738
    Abstract: A method for manufacturing an epitaxial wafer including the steps of: preparing a silicon-based substrate having a chamfered portion in a peripheral portion; forming an annular trench in the chamfered portion of the silicon-based substrate along an internal periphery of the chamfered portion; and performing an epitaxial growth on the silicon-based substrate having the trench formed. This provides a method for manufacturing an epitaxial wafer by which a crack generated in a peripheral chamfered portion can be suppressed from extending towards the center.
    Type: Application
    Filed: September 6, 2019
    Publication date: November 18, 2021
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Keitarou TSUCHIYA, Kazunori HAGIMOTO, Masaru SHINOMIYA
  • Patent number: 11177125
    Abstract: A method for cleaning a semiconductor wafer, including: inserting a semiconductor wafer into a hydrofluoric acid tank filled with hydrofluoric acid to immerse the semiconductor wafer in the hydrofluoric acid; pulling out the semiconductor wafer from the hydrofluoric acid tank; and then inserting the semiconductor wafer into an ozone water tank filled with ozone water to immerse the semiconductor wafer in the ozone water for cleaning. The semiconductor wafer is inserted into the ozone water tank at a rate of 20000 mm/min or more at least after a lower end of the semiconductor wafer comes into contact with the ozone water until the semiconductor wafer is completely immersed in the ozone water. A method for cleaning a semiconductor wafer which can prevent and remove contaminant from re-adhering in a method in which a semiconductor wafer is cleaned by immersion in hydrofluoric acid and then cleaned by immersion in ozone water.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 16, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kensaku Igarashi, Tatsuo Abe
  • Patent number: 11175231
    Abstract: A method for evaluating a carbon concentration where ions of a predetermined element are implanted into a silicon wafer, and then a carbon concentration is measured by a low-temperature PL method from an emission intensity of a CiCs composite, where the ions are implanted under implantation conditions of 1.1×1011×[atomic weight of the implanted element]?0.73<implantation amount (cm?2)<4.3×1011×[atomic weight of the implanted element]?0.73, and the carbon concentration is evaluated. A method for evaluating a carbon concentration makes it possible to measure with high sensitivity, a carbon concentration in a surface layer of 1 to 2 ?m, which is a photodiode region in an image sensor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 16, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Yasushi Mizusawa
  • Patent number: 11149357
    Abstract: A method for manufacturing a SiC single crystal having a growth container surrounded by a heat-insulating material, a seed crystal substrate disposed inside a top at a center of the container, a silicon carbide raw material disposed at a bottom of the container to sublimate and grow a SiC crystal to allow a center of the hole to deviate from a center position of the seed substrate to a position on a periphery side, a SiC substrate having a main surface tilted from a {0001} plane wherein a basal plane is used and grown with the seed substrate so that a direction of a component of a normal vector of the basal plane of the seed substrate parallel to the main surface and an eccentric direction of the hole are opposite directions in a cross-sectional view including the center of the seed substrate and the center of the hole.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 19, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hitoshi Ikeda, Toru Takahashi, Tetsuro Aoyama, Yuichi Matsumoto
  • Publication number: 20210262119
    Abstract: A silicon carbide single crystal growth apparatus including: a growth container including a growth container lid to which a seed crystal substrate is adhered and a growth container body for containing seed crystal substrate and a silicon carbide raw material; a heat-insulating container surrounding growth container; a temperature measuring equipment measuring a temperature inside growth container through a hole for temperature measurement provided in the heat-insulating container; and a heater heating the silicon carbide raw material, where a silicon carbide single crystal is grown on seed crystal substrate by heating and subliming silicon carbide raw material by a sublimation method, where growth container lid has a pattern that penetrates the growth container lid formed only within an adhesion region of the seed crystal substrate on the growth container lid. This provides an apparatus and manufacturing method that can suppress the generation of threading screw, basal plane, and threading edge dislocation.
    Type: Application
    Filed: May 29, 2019
    Publication date: August 26, 2021
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hitoshi IKEDA, Yuichi MATSUMOTO, Toru TAKAHASHI
  • Patent number: 11094525
    Abstract: A method for cleaning a semiconductor wafer, including: supplying a semiconductor wafer whose surface has an oxide film formed thereon with a cleaning solution capable of removing the oxide film; and cleaning, while rotating, the semiconductor wafer to remove the oxide film formed on the surface of the semiconductor wafer. The oxide film is removed such that a rotational speed of the semiconductor wafer is 300 rpm or more after the cleaning with the cleaning solution is started and before a water-repelling surface is attained, and then the rotational speed of the semiconductor wafer is changed to 100 rpm or less to completely remove the oxide film. A method for cleaning a semiconductor wafer by which both surface roughness improvement and surface defect suppression can be achieved.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 17, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Kensaku Igarashi, Tatsuo Abe
  • Publication number: 20210249301
    Abstract: A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 ?·cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 12, 2021
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Toshikazu IMAI, Kazuhiko YOSHIDA, Miho NIITANI, Taishi WAKABAYASHI, Osamu ISHIKAWA