Abstract: A method for manufacturing an epitaxial wafer by forming a single crystal silicon layer on a wafer containing a group IV element including silicon, the method including the steps of: removing a natural oxide film on a surface of the wafer containing the group IV element including silicon in an atmosphere containing hydrogen; forming an oxygen atomic layer by oxidizing the wafer after removing the natural oxide film; and forming a single crystal silicon by epitaxial growth on the surface of the wafer after forming the oxygen atomic layer, where a planar density of oxygen in the oxygen atomic layer is set to 4×1014 atoms/cm2 or less. A method for manufacturing an epitaxial wafer having an epitaxial layer of good-quality single crystal silicon while also allowing the introduction of an oxygen atomic layer in an epitaxial layer stably and simply.

Abstract: An apparatus for manufacturing a single crystal by growing a single crystal according to a Czochralski method, the apparatus including: main chamber configured to house crucible configured to accommodate raw-material melt, and heater configured to heat raw-material melt; pulling chamber continuously provided at upper portion of main chamber and configured to accommodate single crystal grown and pulled; cooling cylinder extending from at least ceiling portion of main chamber toward raw-material melt so as to surround single crystal being pulled, cooling cylinder configured to be forcibly cooled with coolant; and auxiliary cooling cylinder fitted in an inside of cooling cylinder. Auxiliary cooling cylinder is made of any one or more materials of graphite, carbon composite, stainless steel, molybdenum, and tungsten. The auxiliary cooling cylinder has structure covering bottom surface of cooling cylinder facing raw-material melt. Gap between auxiliary cooling cylinder and bottom surface of cooling cylinder is 1.

Abstract: The present invention is a substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has at least a bond wafer including a silicon single crystal joined on a base wafer including a silicon single crystal, the base wafer includes CZ silicon having a resistivity of 0.1 ?cm or lower and a crystal orientation of <100>, and the bond wafer has a crystal orientation of <111>. This provides a substrate for an electronic device, having a suppressed warp.

Abstract: A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 ?·cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.

Abstract: A method evaluates an edge shape of a silicon wafer, in which as shape parameters in a wafer cross section, when defining a radial direction reference L1, a radial direction reference L2, an intersection point P1, a height reference plane L3, h1 [?m], h2 [?m], a point Px3, a straight line Lx, an angle ?x, a point Px0, ? [?m], a point Px1, and a radius Rx [?m], the edge shape of the silicon wafer is measured, values of the shape parameters h1, h2, and ? are set, the shape parameters Rx and ?x are calculated in accordance with the definition based on measurement data of the edge shape, and the edge shape of the silicon wafer is determined from the calculated Rx and ?x to be evaluated. Consequently, a method evaluates an edge shape of a silicon wafer capable of preventing an occurrence of trouble.

Abstract: A method includes: determining height Z1 of a focus by an optical microscope having autofocus function which uses irradiation light of wavelength ?0 to adjust the focus; determining a wavelength ?1 of irradiation light used for obtaining observation image of second thin film; obtaining observation image of second thin film by using irradiation light of the wavelength ?1, while altering heights of the focus with the Z1 as reference point; calculating standard deviation of reflected-light intensity distribution within the observation image, obtaining height Z2 of the focus corresponding to a peak position where standard deviation is greatest, and calculating a difference ?Z between Z1 and Z2; correcting the autofocus function with ?Z as a correction value; and using the corrected autofocus function to adjust the focus, obtaining the observation image of the second thin film, and calculating the film thickness distribution from the reflected-light intensity distribution within the observation image.

Abstract: A carrier for a double-side polishing apparatus configured to double-side polish providing a semiconductor silicon wafer. The carrier being disposed between upper and lower turn tables have a polishing pad attached, and includes a holding hole formed to hold the semiconductor silicon wafer between the upper and lower turn tables during polishing. The carrier for a double-side polishing apparatus is made of a resin. An average contact angle with pure water of front and back surfaces of the carrier, which come into contact with the polishing pads, is 45° or more and 60° or less, and a difference in average contact angles between the front surface and the back surface is 5° or less, which provides a carrier for a double-side polishing apparatus capable of enhancing the polishing rate for a semiconductor silicon wafer by using a resinous carrier; and a double-side polishing apparatus and method which employ the carrier.

Abstract: A method for measuring a wafer profile while holding a periphery of the wafer by using a flatness measurement system, including first and second optical systems respectively located on first and second main surfaces of the wafer, the method including: a first step measuring each surface variation on the main surfaces using one of the optical systems; a second step of calculating a periphery-holding deformation amount, caused by holding the wafer periphery, through utilization of the surface variations measured with the optical system; and a third step of calculating an actual wafer Warp value through subtraction of the periphery-holding deformation amount from a Warp value outputted by the flatness measurement system. This provides a method for measuring a wafer profile to enable measurement of actual wafer Warp value by using a flatness measurement system, and to successfully acquire a Warp value with little influence from a difference among systems.

Abstract: A method for evaluating electrical characteristics of a semiconductor substrate, the method including the steps of: forming a p-n junction on a surface of the semiconductor substrate; mounting the semiconductor substrate on a wafer chuck provided with an equipment for performing light irradiation on the surface of the semiconductor substrate and an equipment for measuring the quantity of the light for the irradiation; performing light irradiation on the surface of the semiconductor substrate for a predetermined time; and measuring an amount of carriers generated after the light irradiation of the p-n junction at least after turning off the light irradiation. This provides a method for evaluating a semiconductor substrate that allows the same evaluation in a wafer state as when an actual solid-state image sensor has been formed without producing a device by using process equipment when evaluating characteristics corresponding to residual image characteristics of a wafer.

Abstract: A method for manufacturing a carbon-doped silicon single crystal wafer, including steps of: preparing a silicon single crystal wafer not doped with carbon; performing a first RTA treatment on the silicon single crystal wafer in an atmosphere containing compound gas; performing a second RTA treatment at a higher temperature than the first RTA treatment; cooling the silicon single crystal wafer after the second RTA treatment; and performing a third RTA treatment. The crystal wafer is modified to a carbon-doped silicon single crystal wafer, sequentially from a surface thereof: a 3C-SiC single crystal layer; a carbon precipitation layer; a diffusion layer of interstitial carbon and silicon; and a diffusion layer of vacancy and carbon. A carbon-doped silicon single crystal wafer having a surface layer with high carbon concentration and uniform carbon concentration distribution to enable wafer strength enhancement; and a method for manufacturing the carbon-doped silicon single crystal wafer.

Abstract: A method for heat-treating a silicon single crystal wafer to control a BMD density thereof to achieve a predetermined BMD density by performing an RTA heat treatment on a silicon single crystal wafer composed of an Nv region in a nitriding atmosphere, and then performing a second heat treatment, the method including: formulating a relational equation for a relation between BMD density and RTA temperature in advance; and determining an RTA temperature for achieving the predetermined BMD density according to the relational equation. Consequently, a method for heat-treating a silicon single crystal wafer for manufacturing an annealed wafer or an epitaxial wafer each having defect-free surface and a predetermined BMD density in a bulk portion thereof.

Abstract: A substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has a plurality of silicon single crystal substrates that are joined and has a thickness of more than 2000 ?m, and the plurality of silicon single crystal substrates are produced by a CZ method and have a resistivity of 0.1 ?cm or lower. This provides: a substrate for an electronic device having a nitride semiconductor film formed on a silicon substrate, where the substrate for an electronic device can suppress a warp and can also be used for a product with a high breakdown voltage; and a method for producing the same.

Abstract: A method for producing an electronic device having a drive circuit including a solar cell structure, the method including the steps of: having a first wafer having solar cell structures on a starting substrate and a second wafer having drive circuits formed, so that either one of the first wafer or the second wafer has a plurality of independent diode circuits and capacitor-function laminated portions; obtaining a bonded wafer by bonding so that the solar cell structures, the diode circuits, the capacitor-function laminated portions, and the drive circuits are superimposed; wiring; and dicing the bonded wafer; thus creating a method for producing an electronic device including a drive circuit, a solar cell structure, and a capacitor-function portion in one chip and having a suppressed production cost; and such an electronic device.

Abstract: A method for slicing a workpiece with a wire saw which includes a wire row formed by winding a fixed abrasive grain wire having abrasive grains secured to a surface thereof around a plurality of grooved rollers, the wire being fed from one of a pair of wire reels and taken up by another, the method including feeding a workpiece to the row for slicing while allowing the wire to reciprocate and travel in an axial direction, thereby slicing the workpiece at a plurality of positions aligned in an axial direction of the workpiece simultaneously. Prior to slicing, an abrasive-grain abrading step wherein the wire is allowed to travel without slicing the workpiece, allowing the wire to rub against itself within the reels, and dressing its surface for 30 minutes or more. The method can dress a fixed abrasive grain wire at low cost and suppress thickness unevenness of wafers.

Abstract: A method for manufacturing a silicon single crystal wafer for a multilayer structure device including: using a silicon single crystal wafer with oxygen concentration of 12 ppma (JEITA) or higher and composing an Nv region; and performing an RTA treatment in a nitrogen-containing atmosphere and a temperature of 1225° C. or higher, a mirror-polish processing treatment, and a BMD-forming heat treatment manufacturing a silicon single crystal wafer having at least a DZ layer with a thickness of 5 to 12.5 ?m and a BMD layer positioned immediately below the DZ layer and a BMD density of 1×1011/cm3 or higher from the silicon single crystal wafer surface. During device formation, the silicon wafer surface stress is absorbed immediately below a surface layer, distortion defects are absorbed by the BMD layer, device formation region strength is enhanced, and surface layer dislocation occurrence and extension is suppressed.

Abstract: A method for manufacturing a wafer product, including the steps of: chamfering a circumferential edge portion of a wafer; lapping or double-side grinding main surfaces thereof; etching; mirror-polishing the main surface; and mirror-polishing the chamfered portion. The chamfered portion has a cross-sectional shape including: a first inclined portion continuous from the first main surface; a first arc portion continuous from the first inclined portion and having a radius of curvature; a second inclined portion continuous from the second main surface; a second arc portion continuous from the second inclined portion and having a radius of curvature; and an end portion connecting the first arc portion to the second arc portion. This provides a method for manufacturing a wafer by which a variation in a chamfered cross-sectional shape in a circumferential direction caused by etching can be suppressed.

Abstract: A double-side polishing method including: disposing a wafer between a polishing pad attached to an upper surface of a lower turn table and a polishing pad attached to a lower surface of an upper turn table provided above the lower turn table; and polishing both sides of the wafer. An absolute value of a difference between a gap at inner circumferential portions of the two polishing pads and a gap at outer circumferential portions thereof is defined as a pad gap. The pad gap is larger when the both sides of the wafer are polished than when the two polishing pads are dressed. This provides a double-side polishing method that simultaneously achieves enhancement of quality level (processing precision) and extension of cloth life.

Abstract: The present invention is a method for producing an electronic device having a drive circuit including a solar cell structure, the method including the steps of: obtaining a bonded wafer by bonding a first wafer having a plurality of independent solar cell structures including a compound semiconductor, the solar cell structures being formed on a starting substrate by epitaxial growth, and a second wafer having a plurality of independent drive circuits formed, so that the plurality of solar cell structures and the plurality of drive circuits are respectively superimposed; wiring the bonded wafer so that electric power can be supplied from the plurality of solar cell structures to the plurality of drive circuits respectively; and producing an electronic device having the drive circuit including the solar cell structure by dicing the bonded wafer. This provides a method for producing an electronic device including a drive circuit and a solar cell structure in one chip and having a suppressed production cost.

Abstract: A method for measuring a resistivity of a silicon single crystal by a four-point probe method including: a first grinding step of grinding at a surface of the silicon single crystal on which the resistivity is measured; a cleaning step of cleaning the silicon single crystal subjected to the first grinding step; a donor-annihilation heat treatment step of heat-treating the silicon single crystal subjected to the cleaning step; and a second grinding step of grinding at least the surface of the silicon single crystal subjected to the donor-annihilation heat treatment step on which the resistivity is to be measured, where the resistivity of the silicon single crystal is measured by the four-point probe method after performing the second grinding step. This provides a method for measuring a resistivity of a silicon single crystal by which stable measurement is possible over a long period of time after a donor-annihilation heat treatment.

Abstract: A double-side polishing method, including: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, interposing the held semiconductor wafer between an upper turn table and a lower turn table each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turn table and a thickness B (mm) of the polishing pad attached to the lower turn table satisfy relations of 1.0?A+B?2.0 and A/B>1.0. This provides a double-side polishing method capable of obtaining a semiconductor wafer in which F-ZDD<0 while controlling the GBIR value to be equal to or smaller than a required value.