Patents Assigned to Shinko Electric Industries Co., LTD
  • Patent number: 11289403
    Abstract: A multi-layer substrate includes: a first insulating layer; a conductor layer that is provided on an upper surface of the first insulating layer and that has a penetrating portion; a second insulating layer that covers the conductor layer and that is stacked on the upper surface of the first insulating layer; a via hole that penetrates the second insulating layer from an upper surface of the second insulating layer to reach an inside of the first insulating layer and that includes the penetrating portion; and an insulating member with which the via hole is filled. The conductor layer has a portion exposed in the via hole, and the insulating member covers an upper surface and a lower surface of the conductor layer exposed in the via hole through the penetrating portion of the conductor layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 29, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Misaki Komatsu, Katsuya Fukase
  • Patent number: 11282771
    Abstract: An electronic component includes a metal member, an inductor, and a encapsulating resin. The metal member has an outer lead, an inner lead provided at a position opposed to the outer lead, and a post connecting the outer lead with the inner lead. The inductor is provided between the outer lead and the inner lead and connected to the outer lead or the inner lead. The encapsulating resin encapsulates the metal member and the inductor.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 22, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki Matsumoto, Tsukasa Nakanishi, Tadaaki Katsuyama
  • Patent number: 11262137
    Abstract: A loop-type heat pipe includes: an evaporator; a condenser; a liquid pipe; and a vapor pipe. The evaporator is formed by layered metal layers that include: a first outermost metal layer; a second outermost metal layer; and an inner layer. The inner layer includes: a first metal layer adjacent to the first outermost metal layer; and a second metal layer adjacent to the second outermost metal layer. At least one space and a porous member are provided in the inner layer. The first metal layer is formed with a first bottomed groove. The second metal layer is formed with a second bottomed groove. One end of the space corresponds to a portion of the first metal layer where the first bottomed groove is formed. The other end of the space corresponds to a portion of the second metal layer where the second bottomed groove is formed.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 1, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yoshihiro Machida
  • Patent number: 11257749
    Abstract: A wiring substrate includes: a core layer having a first face, and a second face opposite to the first face; a through hole that penetrates the core layer; a first metal layer formed on an inner wall face of the through hole and formed on or above the first and second faces; a second metal layer that is formed on the first metal layer and fills the through hole, wherein the second metal layer has a first recess portion opposed to the through hole, and a second recess portion opposed to the first recess portion via the through hole; a third metal layer provided in the first recess portion; a fourth metal layer provided in the second recess portion; a fifth metal layer formed on the second metal layer and the third metal layer; and a sixth metal layer formed on the second metal layer and the fourth metal layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 22, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kazuhiro Tanaka
  • Patent number: 11239196
    Abstract: A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: February 1, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Satoshi Shiraki
  • Patent number: 11230779
    Abstract: A substrate plating method includes forming a first resist film exposing a first feeding layer on a first face of a substrate; forming a second resist film exposing a second feeding layer on a second face of the substrate opposite to the first face; holding the substrate with a clamp member in such a manner that the clamp member is in contact with the first feeding layer and the second feeding layer, and arranging a first electrode in opposed relation with the first face and a second electrode in opposed relation with the second face; and forming a plating layer on a plating-scheduled region of the first face under conditions in which a value of current supplied between the second face and the second electrode is larger than a value of current supplied between the first face and the first electrode.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: January 25, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Katsuya Kubo
  • Patent number: 11233001
    Abstract: An interconnect board includes: a first substrate; a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate. The fillet has a raised portion raised from a level of a top surface of the second substrate to a level higher than the top surface of the second substrate.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: January 25, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Shota Miki, Naoki Kobayashi
  • Patent number: 11227813
    Abstract: An electronic apparatus includes: a first metal layer; an electronic component that is provided on the first metal layer; a second metal layer that is provided on the first metal layer and on the electronic component; and an insulating resin that fills a space between the first metal layer and the second metal layer so as to cover the electronic component. The second metal layer includes: a sheet-like electrode pad portion; and a connection portion that is disposed along a peripheral edge of the electrode pad portion, and that protrudes from the electrode pad portion toward the first metal layer so as to electrically connect the second metal layer to the first metal layer.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: January 18, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki Matsumoto, Tsukasa Nakanishi, Tadaaki Katsuyama
  • Publication number: 20220011055
    Abstract: A flat loop heat pipe includes an evaporator that vaporizes a working fluid, a condenser that liquefies the working fluid vaporized by the evaporator, a vapor pipe that connects the evaporator to the condenser, and a liquid pipe that connects the condenser to the evaporator. The liquid pipe includes a first wick. The condenser includes a flow passage and a second wick. The flow passage connects the vapor pipe and the liquid pipe. The second wick is connected to the first wick. The second wick is exposed in the flow passage and extends from the flow passage in a planar direction.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Applicant: Shinko Electric Industries Co., LTD.
    Inventor: Nobuyuki Kurashima
  • Patent number: 11219128
    Abstract: A laminated structure includes an interconnect structure including first and second product areas and a first interconnect layer, and a first insulating layer formed on the interconnect structure. The first product area includes an opening penetrating the first insulating layer, and the second product area includes an annular groove penetrating the first insulating layer. The laminated structure further includes an electronic component mounted inside the opening in the first product area with an annular gap formed between the electronic component and a wall surface defining the opening, an insulating member located inside the groove in the second product area, a second insulating layer that fills the annular gap and the groove, and covers the first insulating layer, the electronic component, and the insulating member, and a second interconnect layer formed on the second insulating layer, and electrically connected to the first interconnect layer.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: January 4, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Izumi Tanaka
  • Patent number: 11211326
    Abstract: An insulating layer containing fillers is formed to cover a first wiring layer. An opening portion, in which the first wiring layer is exposed, is formed in the insulating layer. A first alkali treatment, an ultrasonic cleaning treatment, and a second alkali treatment are sequentially performed on an upper surface of the insulating layer, on an inner wall surface of the opening portion, and an upper surface of the first wiring layer exposed in the opening portion. A second wiring layer electrically connected to the first wiring layer is formed by filling the opening portion by plating. The second wiring layer extends from an inside of the opening portion to the upper surface of the insulating layer.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 28, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yoshihisa Kanbe, Tomoyuki Shimodaira, Takashi Sato
  • Patent number: 11205632
    Abstract: A wiring substrate includes: a plurality of wiring layers; and a plurality of insulating layers. The wiring substrate includes: a mounting region on which an electronic component is to be mounted; and a non-mounting region on which no electronic component is to be mounted and which is configured to be bent in a first direction. At least one of the wiring layers comprises a shield pattern. The shield pattern disposed in the non-mounting region is defined by a plurality of through holes arranged at predetermined intervals. Each of the through holes has a bent portion bent in plan view.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 21, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kenichi Mori, Takehito Terasawa
  • Publication number: 20210391518
    Abstract: A light emitting device includes a ceramic substrate, a light emitting element, and a wiring. The light emitting element is formed on an upper surface of the ceramic substrate. The wiring is arranged inside the ceramic substrate and is electrically and directly connected to the light emitting element. The light emitting element includes a structure in which a lower semiconductor layer, an active layer, and an upper semiconductor layer are sequentially stacked.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 16, 2021
    Applicant: Shinko Electric Industries Co., LTD.
    Inventors: Michio Horiuchi, Yuichiro Shimizu, Masaya Tsuno
  • Publication number: 20210391508
    Abstract: A light emitting device includes a light-transmissive ceramic substrate, a light emitting element mounted on the ceramic substrate, a wiring arranged inside the ceramic substrate and electrically connected to the light emitting element, a base material faced to the ceramic substrate, and a seal member hermetically sealing a gap between the ceramic substrate and the base material. The light emitting element is arranged in a space surrounded by the ceramic substrate, the base material, and the seal member. The wiring includes a wiring layer extending in a planar direction of the ceramic substrate.
    Type: Application
    Filed: June 12, 2021
    Publication date: December 16, 2021
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Michio Horiuchi, Masaya Tsuno
  • Patent number: 11193717
    Abstract: A loop heat pipe includes a metal layer stack of two outermost metal layers and intermediate metal layers stacked between the two outermost metal layers. The metal layer stack includes an evaporator, a condenser, a vapor pipe, a liquid pipe, and an inlet. The metal layer stack forms a flow passage that circulates the working fluid through the evaporator, the vapor pipe, the condenser, and the liquid pipe. At least one of the two outermost metal layers includes a thin wall portion that forms a portion of a wall of the vapor pipe in the flow passage.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: December 7, 2021
    Assignee: Shinko Electric Industries Co., LTD.
    Inventor: Takahiko Kiso
  • Patent number: 11175707
    Abstract: A heat pipe including a vapor line having a flow path through which a working fluid vapor flows, wherein the vapor line includes walls opposite to each other across the flow path, and a support post disposed in the flow path and spaced apart from the walls, wherein the walls are made of a plurality of metal layers stacked one over another, and the support post is made of a single seamless member having the same thickness as the walls.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: November 16, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yoshihiro Machida
  • Patent number: 11177152
    Abstract: A ceramics substrate includes: a substrate body; and an electric conductor patient that is provided in the substrate body. The substrate body is made of ceramics containing aluminum oxide. The electric conductor pattern is a sintered body that contains tungsten as a main component and further contains nickel oxide, aluminum oxide and silicon dioxide.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 16, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tomotake Minemura
  • Patent number: 11171080
    Abstract: A wiring substrate includes a first insulation layer, an electronic component including a first surface and a second surface which is an opposite surface to the first surface, the electronic component being mounted on the first insulation layer with the first surface facing toward the first insulation layer, and a second insulation layer including a first layer and a second layer. The first layer is formed on the first insulation layer and configured to cover the second surface of the electronic component, and the second layer is stacked on the first layer. The first layer includes therein fillers. At least one of the fillers is in direct contact with the second surface of the electronic component at one side, and is exposed from the first layer and is thus in direct contact with the second layer at the other side.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 9, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takahiko Kiso, Masahiro Kyozuka
  • Patent number: 11171081
    Abstract: A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 9, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tomoaki Machida
  • Patent number: 11158583
    Abstract: A substrate with built-in component includes: a first wiring layer having at least one reference pattern; a first insulating layer formed on the first wiring layer; and an electronic component mounted, in a cavity formed in the first insulating layer, on the first wiring layer, wherein the at least one reference pattern includes at least one first portion crossing a side surface of the electronic component in plan view, and at least one second portion crossing a side surface of the cavity in plan view.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 26, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Nobutaka Aoki