Abstract: A computing system may include a computer-aided design (CAD) face access engine configured to access a CAD object and an imprint-based meshing engine configured to define an imprint region for a face of the CAD object and determine that the imprint region meets constraint criteria. Responsive to a determination that the imprint region meets the constraint criteria, the imprint-based meshing engine may modify the imprint region into an adapted imprint region and generate an output mesh using the adapted imprint region.

Abstract: A computing system may include a metamaterial representation engine configured to represent a metamaterial of a three-dimensional (3D) object as program code. The metamaterial may define an internal geometry of the 3D object and may be configured to be physically constructed via additive manufacturing. Representation of the metamaterial as program code may include assigning a value of a code parameter of the metamaterial as a probability distribution. The computing system may also include a metamaterial analysis engine configured to analyze the metamaterial through the probability distribution assigned for the value of the code parameter of the program code.

Abstract: A method may include implementing a multi-branch neural network configured to predict manufacturing defects on a layer-of-interest of an integrated circuit (IC) design. The implemented multi-branch neural network may include multiple neural network branches, including a layer-of-interest branch that processes inputs of the layer-of-interest, additional design layer branches that process inputs of the other design layers of the IC design different from the layer-of-interest, and a merged branch. The merged branch may receive, as inputs, outputs of the layer-of-interest branch and the additional design layer branches, and the merged branch may be configured to output a predictor value for the IC design.

Abstract: A computing system implementing a physical verification tool can determine principal feature components describing geometric patterns around points of interest in a semiconductor layout design. The principal feature components include topological features indicating whether structures are present around the points of interest, and include dimensional features corresponding to measurements associated with the structures present around the points of interest. The physical verification tool can generate a topological signature for each of the points of interest based on the topological features, and cluster the points of interest into different subsets based on the topological signature.

Abstract: Layout features in a layout design are classified into groups of layout features. A machine learning-based SRAF generation process is then performed to generate sub-resolution assist features for layout features in each of the groups of layout features. Each of the groups of layout features has a specific machine learning model. The machine learning-based SRAF generation process comprising: dividing regions where sub-resolution assist features are likely to be placed into areas of interest, extracting a feature vector for each of the areas of interest based on a layout area centered at the each of the areas of interest, determining whether the each of the areas of interest should be part of a sub-resolution assist feature by using the feature vector as an input of the specific machine learning model, and generating the sub-resolution assist features based on results of the determining.

Abstract: This application discloses a computing system implementing a mask synthesis system to generate synthetic image clips of design shapes and corresponding mask data for the synthetic image clips. The mask data can describe lithographic masks capable of being used to fabricate the design shapes on an integrated circuit. The mask synthesis system can utilize the synthetic image clips of the design shapes and the corresponding mask data to train a machine-learning system to determine pixelated output masks from portions of the layout design. The mask synthesis system can identify one or more pixelated output masks for portions of a layout design describing an electronic system using the trained machine-learning. The mask synthesis system can synthesize a mask layout design for the electronic system based, at least in part, on the layout design describing the electronic system and the one or more pixelated output masks for the layout design.

Abstract: A computing system may include an access engine and a defect detection engine. The access engine may be configured to access a slice contour of a given layer of a 3-dimensional (3D) object designed for manufacture through an additive manufacturing process and obtain hatch tracking for the slice contour, the hatch tracking representative of an energy path to melt metal powder for constructing the given layer through the additive manufacturing process. The defect detection engine may be configured to construct, from the slice contour, an as-built image for the given layer by rendering the hatch tracking in the slice contour; construct, from the slice contour, an idealized image for the given layer; and identify defects in the given layer via image analysis between the as-built image and the idealized image.

Abstract: Various aspects of the present disclosed technology relate to techniques for hotspot root cause determination. Feature values for a plurality of design/process-related features for each of the layout regions of interest on a layout design are determined. Population ratios for feature value ranges for each of the plurality of design/process-related features are determined based on a number of layout regions of interest having feature values within each of the feature value ranges. Hotspot feature repeater values are determined. Based on the population ratios and the hotspot feature repeater values, a root cause analysis can be performed to determine one or more design/process-related features that are most likely causes for each of a plurality of hotspot layout regions. The information of the one or more design/process-related features can be used to identity other hotspot regions and adjust the layout design or to adjust a manufacturing process.

Abstract: This application discloses a computing system (400) to generate a product model (409) that describes attributes of a product including an electronic system (401). The computing system (400) can implement a machine-learning algorithm having been trained with metadata populated in previously generated product models for different electronic systems, which can determine one or more sets of metadata capable of being correlated to the electronic system included in the product model based on the attributes of the electronic system described in the product model. The sets of metadata can correspond to different design constraints in the product model associated with electrical connectivity for the electronic system and their corresponding parameter values. The computing system can populate at least one of the sets of metadata into the product model to correlate with the electronic system.

Abstract: A computing system to parse a schematic design illustrating a circuit design for an electronic system to identify text and enclosures representing circuit devices of the electronic system, The computing system can classify the text based on a proximity of the text to the enclosures in the schematic diagram, and match the text to the enclosures in the schematic diagram based on the classifications, which correlates the circuit devices represented by the enclosures to the text matched to the enclosures. The computing system can identify one of the circuit devices includes a connector having one or more pins, and correlate the text matched to the enclosure to at least one of the pins based on a relative alignment of the pins with the text. The computing system can generate an interactive technical file that includes the correlations of the circuit devices and pins to the text matched to the enclosures.

Abstract: Methods and systems are disclosed for generation of cellular lattice kernels optimized by multiple objectives for highly specific targeted properties of geometry and topology rather than state of the art methods that rely on a predefined kernel library. Using a characterization of virtual kernel features, bulk material properties can be predicted using approximations from the virtual kernel rather than having to rely solely on experimental finite element simulations of lattice structures.

Abstract: A computing system may include a quantifier determination engine configured to determine a defectivity quantifier for a lithographical circuit fabrication process performed with a target value for a process parameter, including by modifying the target value to obtain an off-target value for the process parameter, determining a defectivity quantifier for the lithographical circuit fabrication process performed with the off-target value, and extrapolating the defectivity quantifier for the lithographical circuit fabrication process performed with the target value from the determined defectivity quantifier for the lithographical circuit fabrication process performed with the off-target value. The computing system may also include a quantifier provision engine configured to provide the determined defectivity quantifier for assessment of the lithographical circuit fabrication process.

Abstract: A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second masking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.

Abstract: A computing system may include a design access engine configured to access an injection mold design and a channel construction engine configured to construct conformal cooling channels for the injection mold design. The channel construction engine may do so by extracting a cooling surface of the injection mold design, generating a central offset surface with a same shape as the cooling surface, projecting cooling lines on to the central offset surface, detecting sharp portions of the projected cooling lines, smoothing the detected sharp portions of the projected cooling lines, and generating the conformal cooling channels using the smoothed cooling lines along the central offset surface as a center line for the conformal cooling channels.

Abstract: A computing system implementing a design characterization tool can sample a distribution of values for manufacturing variation of an integrated circuit described by a circuit design. The design characterization tool can order the samples based on predicted output values of the circuit design set with characteristics in the samples of the values for manufacturing variation. The computing system can implement an analog simulator to simulate the circuit design utilizing a subset of the samples of values for manufacturing variation to identify simulated output values for an output distribution model. The design characterization tool can estimate an error in the order of the samples associated with the predicted outputs of the circuit design based on the simulated output values in the output distribution model. The design characterization tool can modify the output distribution model to correct a bias based on the estimated error in the order of the samples.

Abstract: A preliminary netlist comprising the photonic devices and location and rotation information for each of the photonic devices is extracted from the original layout design. In the extraction, each of the photonic devices is treated as a black box. A geometric pattern for the each of the photonic devices is then identified in a group of geometric patterns for each of the photonic devices based on physical properties of the each of the photonic devices specified in the circuit design. A new layout design is generated based on the identified geometric pattern for each of the photonic devices, the location and rotation information for each of the photonic devices, and the preliminary netlist. Geometric elements in each of the photonic devices in the new layout design are compared with corresponding geometric elements in the original layout design.

Abstract: This application discloses a server to transmit an embedded application to a remote gateway device. The embedded application, when executed, prompts the remote gateway device to generate application messages including information associated with the execution of the embedded application by the remote gateway device. The server is configured to track the execution of the embedded application in the remote gateway device to determine operational states of the embedded application based, at least in part, on the application messages received from the remote gateway device. The server is configured to generate a parameter message for transmission to the remote gateway device based, at least in part, on the operational states of the embedded application deployed in the remote gateway device. The parameter message is configured to prompt the remote gateway device to transmit an application parameter associated with the execution of the embedded application.

Abstract: A computing system may include a client device and a server. The client device may be configured to access a stream of image frames that depict an environment, determine, from the stream of image frames, environment images that satisfy selection criteria, and transmit the environment images to the server. The server may be configured to receive the environment images from the client device, construct a spatial view of the environment based on position data included with the environment images, and navigate the spatial view, including by receiving a movement direction and progressing from a current environment image depicted for the spatial view to a next environment image based on the movement direction.

Abstract: This application discloses distributed forward error correction in hardware assisted verification platforms (300) including a hardware-assisted verification system (320) to emulate an electronic system (322) described by a circuit design (301). The hardware-assisted verification system (320) can implement forward error correction circuitry (324) to analyse a data packet (311) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301), which can identify that the data packet includes one or more corrupted bits (321). The forward error correction circuitry (324) can transmit the corrupted data packet (321) to a computing system (330) implementing an error correction algorithm configured to perform error correction operations (332) on the corrupted data packet (321).