Abstract: A system and method for scheduling optical proximity correction (OPC) or other resolution enhancement technique (RET) operations on a layout design is disclosed. A layout design is divided into a plurality of regions, such as a plurality of tiles. OPC is performed on the plurality of tiles in order to generate a modified layout design. Performing OPC on the plurality of tiles may be time consuming. In order to more efficiently distribute the processing of OPC, estimates of OPC processing times for the plurality of tiles is performed. The estimate of the OPC processing time for a respective tile may be based on one or both of analysis of: analysis of the respective tile; or analysis of tile(s) that neighbor the respective tile. Based on the estimates, tiles that have a longer estimated processing tile are scheduled before tiles that have a shorter estimated processing time, thereby potentially resulting in more efficient OPC processing.

Abstract: This application discloses a computing system implementing a reliability verification tool to identify a portion of a layout design describing an integrated circuit includes a victim transistor having a gate connected to an aggressor transistor. The reliability verification tool can extract a resistance network for connections between the victim transistor and the aggressor transistor, and simulate the resistive network to determine connectivity between the wells of the victim transistor and the aggressor transistor occurs prior to the victim transistor having a gate connected to an aggressor transistor.

Abstract: A computing system can obtain wafer images of integrated circuitry having physical structures and classify each of the wafer images based on image characteristics of the wafer images. The computing system can partition each of the wafer images into a plurality of blocks, analyze each of the blocks to determine which of the blocks correspond to a background portion or a contour portion of the wafer images, assign an image score to each wafer image based on the analysis of each of the blocks, and classify the wafer images based on the image scores assigned to the wafer images. The computing system can set parameters for contour extraction using at least one of the wafer images selected from each of the classifications of the wafer images, and extract contours corresponding to the physical structures of the integrated circuitry from the wafer images based, at least in part, on the parameters.

Abstract: An address-skipping trim search performed by a memory built-in self-test system comprises: perform memory read operations on one memory bank to determine whether it fails to correctly sense values of stored data based on a reference trim value for a previous memory bank; if the present memory bank fails, perform memory read operations to search for a new reference trim value for the present memory bank; or otherwise, treat the present reference trim value as the one for the present memory bank and proceed to testing a next memory bank. The range for searching for the new reference trim value can be limited by the present reference trim value.

Abstract: Aspects of the disclosed technology relate to techniques for achieving optical proximity correction. Anchor points in a layout design may be designated as more important or less important. Optical proximity correction iterations are performed on each of the plurality of regions to generate a modified layout design by processing the more important anchor points differently than the less important anchor points, such as by different weighting or by dynamically changing the target for the less important anchor points. In this way, the edge placement error may be reduced or eliminated for the more important anchor points.

Abstract: A computing system may include a voxel access engine configured to access voxel data and a voxel processing engine. The voxel processing engine may identify and label thin features in the voxel data, smooth the voxel data to preserve the thin features, and convert the voxel data to form a faceted representation. The voxel processing engine may also adaptively perform a pressing process on the faceted representation. Responsive to a determination that a pressing reapplication criterion is satisfied, the voxel processing engine may modify the voxel data, convert the modified voxel data to form the faceted representation of the object, and perform the pressing process on the faceted representation of the object formed through the modified voxel data.

Abstract: A circuit comprises: a plurality of identical circuit blocks, each of the plurality of identical circuit blocks comprising one or more test output ports; a first bit-combining device and a second bit-combining device for each of the one or more test output ports; a delay device for each of the one or more test output ports; and a network coupled to each of the plurality of identical circuit blocks and configured to transport a first bit stream and a second bit stream during a test, wherein the first bit-combining device and the second bit-combining device are configured to combine bits outputted from the each of the one or more test output ports with bits of the first bit stream and bits of the second bit stream that are delayed by the delay device, respectively.

Abstract: A method and apparatus for designing and manufacturing a component in a computer-aided design and manufacturing environment is disclosed. A method includes obtaining a geometric model of a component from a geometric model database, and determining at least one orientation parameter value associated with the geometric model of the component. The at least one orientation parameter value is associated with an orientation parameter that defines orientation of the component during additive manufacturing of the component. The method includes performing volumetric analysis of the component based on the at least one orientation parameter value associated with the component using the geometric model of the component.

Abstract: A computer-implemented method of indexing a hierarchical data structure or product structure is disclosed. For a product structure including a product and a plurality of items associated with the product, each item shares a parent-child relationship with at least one other item or the product. The method includes generating a packed configuration-independent index of the product structure by enumerating an unconfigured item-path from the product to an item for each item. Then, when one or more unconfigured item-paths are identical, only one of the identical unconfigured item-paths is maintained. The index may also be combined with an unconfigured item-path spatial-bounds index. Both product structure and spatial location queries may be filtered against the combined index.

Abstract: A method may support realistic test circuit generation through random circuit layer blocks. The method may include accessing a set of circuit layer blocks, performing a block-level design rule check (DRC) process on the set of circuit layer blocks, wherein the block-level DRC process applies selected design rules that are a subset of a design rule set for a circuit manufacturing process, and obtaining a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process. The method may also include generating a test circuit layer formed through randomly selected circuit blocks from the set of clean circuit layer blocks and utilizing the test circuit layer in support of testing the circuit manufacturing process.

Abstract: Text containers comprising information of cell ports are determined based on statements for cell ports in a rule file. Drawn layers comprising cell ports are determined based on the determined text containers or based on statements for attaching each of the test containers to a layout design layer in the rule file. Layout design layers connected to the drawn layers comprising cell ports are determined based on statements for connecting layout design layers in the rule file. A file for cell port detection is generated which associates each of the text containers comprising information of cell ports with one or more of the drawn layers comprising cell ports and one or more of the layout design layers connected to the one or more of the drawn layers comprising cell ports. The file for cell port detection can be used for extracting ports for cells to be black boxed.

Abstract: A computing system may include a logic construction engine configured to construct, via multi-level prediction, workflow logic to process a computer-aided design (CAD) model. The logic construction engine may do so by identifying a multi-node sequence inserted into the workflow logic, aggregating past workflow data specific to the multi-node sequence, determining a node prediction in the workflow logic for the multi-node sequence based on the aggregated past workflow data, and providing the node prediction as a suggested insertion for the workflow logic.

Abstract: A computing system may include a computer-aided design (CAD) face access engine configured to access a CAD object and an imprint-based meshing engine configured to define an imprint region for a face of the CAD object and determine that the imprint region meets constraint criteria. Responsive to a determination that the imprint region meets the constraint criteria, the imprint-based meshing engine may modify the imprint region into an adapted imprint region and generate an output mesh using the adapted imprint region.

Abstract: A computing system may include a metamaterial representation engine configured to represent a metamaterial of a three-dimensional (3D) object as program code. The metamaterial may define an internal geometry of the 3D object and may be configured to be physically constructed via additive manufacturing. Representation of the metamaterial as program code may include assigning a value of a code parameter of the metamaterial as a probability distribution. The computing system may also include a metamaterial analysis engine configured to analyze the metamaterial through the probability distribution assigned for the value of the code parameter of the program code.

Abstract: A method may include implementing a multi-branch neural network configured to predict manufacturing defects on a layer-of-interest of an integrated circuit (IC) design. The implemented multi-branch neural network may include multiple neural network branches, including a layer-of-interest branch that processes inputs of the layer-of-interest, additional design layer branches that process inputs of the other design layers of the IC design different from the layer-of-interest, and a merged branch. The merged branch may receive, as inputs, outputs of the layer-of-interest branch and the additional design layer branches, and the merged branch may be configured to output a predictor value for the IC design.

Abstract: A computing system implementing a physical verification tool can determine principal feature components describing geometric patterns around points of interest in a semiconductor layout design. The principal feature components include topological features indicating whether structures are present around the points of interest, and include dimensional features corresponding to measurements associated with the structures present around the points of interest. The physical verification tool can generate a topological signature for each of the points of interest based on the topological features, and cluster the points of interest into different subsets based on the topological signature.

Abstract: Layout features in a layout design are classified into groups of layout features. A machine learning-based SRAF generation process is then performed to generate sub-resolution assist features for layout features in each of the groups of layout features. Each of the groups of layout features has a specific machine learning model. The machine learning-based SRAF generation process comprising: dividing regions where sub-resolution assist features are likely to be placed into areas of interest, extracting a feature vector for each of the areas of interest based on a layout area centered at the each of the areas of interest, determining whether the each of the areas of interest should be part of a sub-resolution assist feature by using the feature vector as an input of the specific machine learning model, and generating the sub-resolution assist features based on results of the determining.

Abstract: This application discloses a computing system implementing a mask synthesis system to generate synthetic image clips of design shapes and corresponding mask data for the synthetic image clips. The mask data can describe lithographic masks capable of being used to fabricate the design shapes on an integrated circuit. The mask synthesis system can utilize the synthetic image clips of the design shapes and the corresponding mask data to train a machine-learning system to determine pixelated output masks from portions of the layout design. The mask synthesis system can identify one or more pixelated output masks for portions of a layout design describing an electronic system using the trained machine-learning. The mask synthesis system can synthesize a mask layout design for the electronic system based, at least in part, on the layout design describing the electronic system and the one or more pixelated output masks for the layout design.

Abstract: A computing system may include an access engine and a defect detection engine. The access engine may be configured to access a slice contour of a given layer of a 3-dimensional (3D) object designed for manufacture through an additive manufacturing process and obtain hatch tracking for the slice contour, the hatch tracking representative of an energy path to melt metal powder for constructing the given layer through the additive manufacturing process. The defect detection engine may be configured to construct, from the slice contour, an as-built image for the given layer by rendering the hatch tracking in the slice contour; construct, from the slice contour, an idealized image for the given layer; and identify defects in the given layer via image analysis between the as-built image and the idealized image.

Abstract: Various aspects of the present disclosed technology relate to techniques for hotspot root cause determination. Feature values for a plurality of design/process-related features for each of the layout regions of interest on a layout design are determined. Population ratios for feature value ranges for each of the plurality of design/process-related features are determined based on a number of layout regions of interest having feature values within each of the feature value ranges. Hotspot feature repeater values are determined. Based on the population ratios and the hotspot feature repeater values, a root cause analysis can be performed to determine one or more design/process-related features that are most likely causes for each of a plurality of hotspot layout regions. The information of the one or more design/process-related features can be used to identity other hotspot regions and adjust the layout design or to adjust a manufacturing process.