Abstract: A computing system implementing a design characterization tool can sample a distribution of values describing manufacturing variation for an integrated circuit described by a circuit design. The design characterization tool can utilize a set of the samples to generate a surrogate model of the circuit design, and can order another set of the samples based on predicted outputs of the surrogate model. The design characterization tool can simulate the surrogate model or the circuit design utilizing the ordered samples, and stop the simulations prior to all of the samples from the distribution having been utilized in the simulations. The design characterization tool can utilize a confidence interval stopping condition or a drought stopping condition to determine when to stop the simulations. The design characterization tool can utilize results of the simulations to characterize operational variation of the circuit design to the manufacturing variation described in the distribution of the values.

Abstract: A system may include a set of compute engines. The compute engines may be configured to perform electronic design automation (EDA) operations on a hierarchical dataset representative of an integrated circuit (IC) design. The system may also include a dynamic resource balancing engine configured to allocate computing resources to the set of compute engines and reallocate a particular computing resource allocated to a first compute engine based on an operation priority of an EDA operation performed by a second compute engine, an idle indicator for the first compute engine, or a combination of both.

Abstract: A computer-aided design (CAD) system may support anti-constraint configuration and enforcement for CAD models that represent physical objects. Anti-constraints may specify given constraints not to be applied for components of the CAD model, and the CAD system may update components of the CAD model without applying the constraints specified in anti-constraints applicable to the CAD model components.

Abstract: A method of modifying a CAD system model performed on a data processing system includes receiving a dataset of co-ordinates representing an article in 2d, or in 3d and receiving 2d or 3d constraints respectively, to be applied to any changes to the dataset of co-ordinates for the article. A modification to be applied to the dataset is received and combined with the relevant 2d and 3d constraints to produce a constrained modification for each of the article and associated article. The constrained modification is solved in 2d and in 3d to determine whether a solution exists in which all constraints are met. If the solve is successful, the constrained modification is applied to each dataset simultaneously and, updated datasets are stored. If the solve fails, the constraints may be reduced and the solve step repeated, or the process is terminated.

Abstract: A testing circuit configured to test and diagnose a read-only memory comprises two multiple-input signature registers configured to generate two sets of signatures for multiple iterations of reading some or all of words stored in the read-only memory, control circuitry configured to control, according to a test algorithm, from which of the outputs of the read-only memory each of the two multiple-input signature registers receives test response signal bits for each of the reading operations during each of the iterations, and a faulty element location determination device configured to generate a faulty element location signal for the read-only memory based on results of comparing the two sets of signatures with reference signatures.

Abstract: A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A computing system may include an initial design space engine and an active region adaptation engine. The initial design space engine may be configured to identify a design domain for which to optimize a topology based on an objective function and determine an active region. The active region adaptation engine may be configured to iteratively adapt the active region until an optimization ending criterion is satisfied. Iterative adaptation of the active region may include expanding the design domain to include branch design elements, performing finite element analysis (FEA) on the expanded design domain, and determining an adapted active region by activating some of the branch design elements based on an active sensitivity threshold and deactivating some of the active design element based on design variable value changes.

Abstract: A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute instructions during clock cycles of the processor. The instruction execution of the processor is monitored by counting the number of successive instructions which are retired contiguously in time to form an instruction count, and counting the number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count. A trace message is generated which includes the instruction count and the stall count, and the trace message is outputted.

Abstract: A computing system may include a circuit design access engine configured to access a circuit design. The computing system may also include a duplicate section processing engine configured to partition the circuit design into multiple circuit sections and determine, from among the multiple circuit sections, an identical section set based on duplicate criteria. Circuit sections of the identical section set may satisfy the duplicate criteria with respect to one another. The duplicate section processing engine may further be configured to perform an OPC processing operation on a selected circuit section of the identical section set and apply an OPC result of the performed OPC processing operation for other circuit sections of the identical section set instead of or without performing the OPC processing operation on the other circuit sections of the identical section set.

Abstract: This application discloses a computing system implementing a design verification tool to perform functional verification on a circuit design describing an electronic device and collect samples of performance data during the functional verification. The computing system can also include a performance visualization tool to generate a profile presentation based on the samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot. The performance visualization tool can receive a data reduction request based on the performance hotspot annunciated by the profile presentation. The data reduction request can identify a subset of the performance data in the profile presentation. The performance visualization tool can generate a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.

Abstract: A computing system may include a model access engine configured to access a CAD model comprised of multiple CAD parts. The computing system may also include a model explosion engine configured to construct a blocking data structure for the CAD model that stores a blocking state for each pair of CAD parts of the CAD model (210) as well as an explosion graph for the CAD model. Iterative generation of the explosion graph by the model explosion engine may include querying the blocking data structure to determine unblocked CAD parts for which to insert a node into the explosion graph. The model explosion engine may also be configured to generate an exploded view representation of the CAD model using the constructed explosion graph.

Abstract: Various aspects of the present disclosed technology relate to techniques for classifying layout patterns. First, a set of density feature vectors for a set of layout regions in the layout design are extracted using a set of rings. Each component of a density feature vector in the set of density feature vectors corresponds to a ring in the set of rings. The set of rings do not overlap with each other and cover a whole area of a circle when being placed together. Next, a machine learning-based clustering process is performed to separate layout features in the set of layout regions into clusters of layout features based on the set of density feature vectors. Each of the clusters of layout features may be further divided into subclusters based on one or more properties.

Abstract: A method of testing radio equipment is disclosed herein. The method includes: receiving, by way of a radio channel test apparatus, a baseband signal representing I/Q data of one or more radio channels; processing, by way of the radio channel test apparatus, the baseband signal representing I/Q data according to one or more radio channel models; and transmitting, by way of the radio channel test apparatus, the processed baseband data representing I/Q data to a radio equipment under test.

Abstract: A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.

Abstract: A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if th

Abstract: System and method for differentiable networks trainable to learn an optimized query of a 3D model database used for object recognition includes training a first differentiable network configured as a differentiable renderer by generating 2D images from 3D models of a first object of a dissimilar second object while optimizing rendering parameters for producing 2D images by gradient descent of a first triple loss function. Visual variation among the images is maximized. A second differentiable network configured as a convolutional neural network defined by a regression function is trained by generating searchable feature vectors of the 2D images. The feature vectors are determined using optimized neural network parameters determined by gradient descent of a second triple loss function to achieve high correlation to an input image of the first object and low correlation to images of the second object.

Abstract: A method of protocol processing including a main program code that has one or more code segments and instructions for processing different protocol elements of a data packet stream of a transport protocol is disclosed herein. The method includes assigning a latency requirement and/or bandwidth requirement to one or more of the code segments of the main program code; and compiling each of the code segments according to the assigned latency and/or bandwidth requirement into a respective target code for executing each of the target codes by different processors.

Abstract: A circuit comprises: a first clock gating device clocked by a first clock signal and configured to generate first clock pulses when a shift enable signal is active, a first transition detecting device clocked by a second clock signal and configured to generate shift gating pulses when detecting active transitions of the first clock pulses, a second clock gating device clocked by the second clock signal and configured to generate shift clock pulses based on the shift gating pulses to clock second scan elements for a shift operation with first scan elements clocked by the first clock signal, and a first retiming device triggered by active pulse edges of the first clock signal and configurable to hold a value for the shift operation. The circuit may further comprise a delay generating device configured to generate delayed shift gating pulses for generating the shift clock pulses.

Abstract: A computing system may include an assembly access engine configured to access a computer-aided design (CAD) assembly that digitally represents a product component that includes multiple parts. The computing system may also include a part determination engine configured to determine a recommended part for the CAD assembly, including by providing the CAD assembly as an input to a machine-learning (ML) model trained with assembly structure data of CAD assemblies of a common product type as the CAD assembly, generating a candidate part set through the ML model, filtering the candidate part set based on physical and cost characteristics of the different candidate parts of the candidate part set, and identifying the recommended part from the filtered candidate part set. The part recommendation engine may also be configured to insert the recommended part into the CAD assembly and provide the CAD assembly in support of physical manufacture.