Abstract: A computer-aided design (CAD) system may support spatially-aware detection of trapped support areas in 3D printing. The CAD system may detect trapped support areas in the surface mesh in that detected trapped support area do not have linear access to an opening in the surface mesh, including by surrounding the surface mesh with a virtual bounding box that encloses the surface mesh, mapping the virtual bounding box and surface mesh into a 3D cube space, and tracking mesh cubes and bounding cubes of the 3D cube space. For a given mesh face of the surface mesh, The CAD system may determine whether the given mesh face is part of a trapped support area by projecting a ray from the given mesh face and assessing the given mesh face as part of a trapped support area based on the ray passing through a mesh cube or a bounding cube.

Abstract: A single radio equipment test device includes a control unit for testing a plurality of antennas, (e.g., an antenna array). The control unit includes a first interface to operatively couple the control unit to an antenna under test, (e.g., arranged in a test chamber). The control unit further includes a second interface to operatively couple the control unit to a reference antenna, (e.g., also arranged in the test chamber). The control unit is configured to control and/or monitor the antenna under test and the reference antenna.

Abstract: A system may support augmented reality (AR)-based layup of plies to form a composite laminate. The system may include an AR headset configured to drive an AR view that digitally visualizes ply placement data on a composite part layup tool physically visible through the AR headset. The system may also include an AR ply layup engine AR ply layup engine configured to analyze a view of the AR headset to identify the composite part layup tool, obtain ply placement data, and provide ply placement data to the AR headset to digitally overlay on the composite part layup tool physically visible through the AR headset.

Abstract: A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.

Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

Abstract: A computer-implemented method is provided for determining a cut pattern of a lathe. The lathe is numerically controlled by a control device and includes a tool with a cutter acting on a workpiece. The workpiece has a start contour and a target contour to be achieved by cutting the workpiece according to the cut pattern. The method includes determining a path of a n-th layer of the cut pattern, wherein the n-th layer includes: for n?2: an infeed path linear and/or parallel to the target contour; a circular infeed path starting tangent to the target contour; an intermediate path linear and/or parallel to the target contour; a circular outfeed path ending tangent to the target contour; and for n?2: a smoothing path linear and/or parallel to the target contour.

Abstract: Systems and methods for process design and analysis of processes that result in products or analytical information are provided. A hypergraph data store is maintained and comprises versions of each process. A version comprises a hypergraph with nodes, for stages of the process, and edges. Stages have parameterized resource inputs associated with stage input properties, and input specification limits. Stages have resource outputs with output properties and output specification limits. Edges link the outputs of nodes to the inputs of other nodes. A run data store is maintained with a plurality of process runs, each run identifying a process version, values for the inputs of nodes in the corresponding hypergraph, their input properties, resource outputs of the nodes, and obtained values of output properties of the resource outputs.

Abstract: A circuit comprises a plurality of clock control devices. Each of the clock control devices is configured to generate a scan test clock signal for a particular clock domain in the circuit and comprises circuitry configured to select clock pulses of a fast clock signal as scan capture clock pulses for the particular clock domain based on a particular clock pulse of a slow clock signal and a scan enable signal. The order and spacing between the groups of the scan capture clock pulses for different clock domains correspond to the order and spacing of the clock pulses of the slow clock signal.

Abstract: Systems and methods may support build direction-based partitioning for construction of a physical object through additive manufacturing. In some implementations, a system may access a surface mesh representative of a 3D object and an initial build direction for construction of the object using additive manufacturing. The system may partition the surface mesh into an initial buildable segment and a non-buildable segment based on the initial build direction. The system may iteratively determine subsequent build directions and partition off subsequent buildable segments from the unbuildable segment until no portion of the non-buildable segment remains. The determined buildable segments and correlated build directions may be provided to a multi-axis 3D printer for construction of the represented 3D object through additive manufacturing.

Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

Abstract: Systems and methods to semantically compare product configuration models. A method includes receiving a first configuration model and a second configuration model. The method includes generating a first order logic (FOL) representation of the first configuration model and an FOL representation of the second configuration model. The method includes performing a satisfiability modulo theories (SMT) solve for nonequivalence satisfiability on the FOL representation of the first configuration model and the FOL representation of the second configuration model. The method includes storing an indication that the first configuration model is equivalent to the second configuration model when the SMT solve for nonequivalence satisfiability is not satisfied.

Abstract: A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

Abstract: This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes.

Abstract: Methods for modeling of parts with lattice structures and corresponding systems and computer-readable mediums. A method includes receiving a model of an object to be manufactured. The method includes receiving a user specification of a void region within the model to create a lattice. The method includes performing a trimming operation to create a trimmed lattice by tessellating void surfaces and grouping together at least one row of connected rods to be treated as a single entity.

Abstract: Systems and a method for simulating a flexible retraction cable during motion of an object to which the cable is attached. The method includes receiving information inputs, including a numerical model of the object, receiving cable information inputs and retraction system information inputs. A numerical model of the flexible cable is modeled by modelling only a part of the flexible cable located outside a retraction system as a sequence of control points distributed along a length of the part, wherein each of the control points is submitted to a force representing the interaction of the control point with its environment and wherein the number of control points is fixed. The method further includes storing the numerical model of the flexible cable in a memory and simulating a motion of the flexible cable that would occur during a movement of the object.

Abstract: A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin. A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.

Abstract: Systems and methods for analyzing information are provided in which a plurality of attribute records are stored. Each respective record in at least a subset of the plurality of records comprises a corresponding unique identifier, a superior/inferior attribute reference, and a heritage indicator. A superior/inferior attribute reference of a first record in the plurality of records references a unique identifier of a second record that is different than the first record, thereby indicating that the first record is a nested attribute record of the second record. Moreover, a heritage indicator of the first record references: the corresponding unique identifier of a third record, thereby indicating that the third record is an ancestor record of the first record, or a unique identifier of a first attribute class record, thereby identifying an attribute class record, in a plurality of attribute class records, to which the first record belongs.

Abstract: A scan network configured to transport repair information between memories and a controller for a non-volatile storage device comprises: repair registers coupled in parallel to repair information generation circuitry for one of the memories and segment selection devices that divide the repair registers into repair register segments. Each of the segment selection devices comprises: a storage element configured to store a segment selection bit and segment selection bit generation circuitry configured to generate the segment selection bit based on the repair information. Each of the segment selection devices is configurable to include or not include the corresponding repair register segment in a scan path of the scan network in a shift operation based on the segment selection bit.

Abstract: Methods for CAD operations and corresponding systems (2800) and computer-readable mediums (2826) are disclosed herein. A method includes receiving (502) a model (600) of a part to be manufactured, wherein the model includes a plurality of original faces (102, 104, 106, 112, 114). The method includes classifying (510) each face in model according to a relative face curvature according to classifications that include at least a high-curvature classification (702). The method includes classifying (514) any sliver faces (102, 104, 106, 112, 114) and narrow blend faces (402, 404, 406, 408) of the plurality of faces. The method includes merging (516) contiguous faces (702) in each classification. The method includes detecting (518) special faces (1002, 1012) of the plurality of faces. The method includes restoring (520) original faces in the high-curvature classification except for the special faces (1002, 1012).

Abstract: Product data management (PDM) systems, methods, and computer-readable media. A method includes receiving a solid body in a PDM data processing system. The method includes determining an operation to perform on the solid body and a target region of the solid body. The method includes moving the target region into a secondary solid body and removing the geometries from the secondary solid body. The method includes generating new geometries corresponding to the operation and the secondary solid body, and applying the new geometries to the topological entities of the secondary solid body. The method includes transforming the adjoining regions to a new position according to the operation. The method includes knitting the transformed adjoining regions to the modified secondary solid body to produce a processed solid body.