Abstract: A method of protocol processing including a main program code that has one or more code segments and instructions for processing different protocol elements of a data packet stream of a transport protocol is disclosed herein. The method includes assigning a latency requirement and/or bandwidth requirement to one or more of the code segments of the main program code; and compiling each of the code segments according to the assigned latency and/or bandwidth requirement into a respective target code for executing each of the target codes by different processors.

Abstract: A circuit comprises: a first clock gating device clocked by a first clock signal and configured to generate first clock pulses when a shift enable signal is active, a first transition detecting device clocked by a second clock signal and configured to generate shift gating pulses when detecting active transitions of the first clock pulses, a second clock gating device clocked by the second clock signal and configured to generate shift clock pulses based on the shift gating pulses to clock second scan elements for a shift operation with first scan elements clocked by the first clock signal, and a first retiming device triggered by active pulse edges of the first clock signal and configurable to hold a value for the shift operation. The circuit may further comprise a delay generating device configured to generate delayed shift gating pulses for generating the shift clock pulses.

Abstract: A computing system may include an assembly access engine configured to access a computer-aided design (CAD) assembly that digitally represents a product component that includes multiple parts. The computing system may also include a part determination engine configured to determine a recommended part for the CAD assembly, including by providing the CAD assembly as an input to a machine-learning (ML) model trained with assembly structure data of CAD assemblies of a common product type as the CAD assembly, generating a candidate part set through the ML model, filtering the candidate part set based on physical and cost characteristics of the different candidate parts of the candidate part set, and identifying the recommended part from the filtered candidate part set. The part recommendation engine may also be configured to insert the recommended part into the CAD assembly and provide the CAD assembly in support of physical manufacture.

Abstract: A computing system may include a design space access engine configured to access a design space of a physical structure. The computing system may also include a structural design engine configured to encode the design space into a set of 3-dimensional (3D) rectangles. Each 3D rectangle may define candidate beam locations in the physical structure and candidate beam locations of the 3D rectangles may be defined by lines between vertex pairs of each 3D rectangle. The structural design engine may also provide the encoded design space as an input to a machine-learning (ML) model, generate, through the ML model, a design of the physical structure based on the encoded design space, and provide the design of the physical structure in support of manufacture of the physical structure.

Abstract: A computing system implementing a design verification system can classify a mixed-signal circuit design describing an electronic device based on a design topology of the mixed-signal circuit design. This classification can be performed by identifying a top-level design block in the mixed-signal circuit design, traversing a connectivity of a design hierarchy to identify lower-level design blocks in the mixed-signal circuit design, and classifying the mixed-signal circuit design based on at least one of a design type of the top-level design block, design types of the lower-level design blocks, or a connectivity of design blocks in the mixed-signal circuit design. The design verification system can selectively partition the mixed-signal circuit design into an analog partition and a digital partition based on the classification, and simulate the analog partition of the mixed-signal circuit design with an analog simulator and the digital partition of the mixed-signal circuit design with a digital simulator.

Abstract: A method is provided for generating test data for testing radio equipment. The method includes: determining, by a test apparatus, one or more beam identifiers; selecting, by the test apparatus, based on the one or more beam identifiers, one or more radio channel models; receiving, by the test apparatus, a baseband signal representing I/Q data of one or more beamforming antennas; processing, by the test apparatus, the baseband signal representing I/Q data according to the selected radio channel model; and transmitting, by the test apparatus, the processed baseband signal representing I/Q data to a radio equipment under test.

Abstract: Systems, methods, logic, and devices may support shoe design through 2.5-dimensional (2.5D) shoe models. In some examples, a system may include a 2D shoe shell pattern engine configured to access a 2D shoe shell pattern, the 2D shoe shell pattern generated for shoe design. The system may also include a 2.5D shoe model engine configured to generate a 2.5D shoe model by placing shoe design elements provided by a user onto the 2D shoe shell pattern of the shoe, including by adding 2.5D layering data for each shoe design element placed on the 2D shoe shell pattern to form the 2.5D shoe model, and wrap the 2.5D shoe model into a 3D shoe model for construction of a physical shoe from the 3D shoe model.

Abstract: Surface editing is performed in typical computer-aided design (CAD) software products by using special tools to edit special surfaces, such as b-splines or subdivision surfaces. It is recognized herein that current approaches to editing surfaces are not generally applicable. For example, common CAD and surface modeling software products are tailored to a specific surface type or vendor specific format, or otherwise are not generally applicable to given analytical and non-analytical surfaces. In various embodiments described herein, subdivision surfaces can be generated to represent any surface. Further, surfaces can be manipulated using a control cage associated with the subdivision surface.

Abstract: Methods for CAD operations and corresponding systems (2100) and computer-readable mediums (2126) are disclosed herein. A method (2000) includes receiving model data (2002) of a surface (210) of a part (200) to be manufactured. The method includes performing a loop-paving process (2004) for a first portion of the surface (210) to produce a first set of elements (302, 304, 306). The method includes performing a Cartesian meshing process (2010) for a second portion of the surface (210) to produce a second set of elements (704). The method includes performing a subdivision meshing process (2016) for a third portion of the surface (210) to produce a third set of elements (1002). The method includes combining (2020) the first set of elements (302, 304, 306), the second set of elements (704), and the third set of elements (1002) to produce a final mesh (1202) for the surface (210) of the part (200) to be manufactured.

Abstract: This application discloses a computing system implementing a power estimator can read in waveform data generated during functional verification of a circuit design describing an electronic device, detect toggles in the signals of the waveform data, correlate the detected toggles in the signals to arcs associated with logic gates in the circuit design, and track a number of times each of the arcs has been correlated to the detected toggles. After the waveform data has been read, the power estimator can look-up power values for each arc having been correlated to a detected signal toggle, multiple the power values by the tracked number of times each of the arcs been correlated to the detected toggles to compute power estimates, and generate an estimate of power consumption for the circuit design during the functional verification by accumulating the power estimates for the arcs associated with the logic gates.

Abstract: A computing system may include an access engine and a heat-aware toolpath engine. The access engine may be configured to access a slice of a 3-dimensional (3D) computer-aided design (CAD) object, wherein the 3D CAD object represents a physical part and wherein the slice represents a physical layer for 3D printing of the physical part. The heat-aware toolpath engine may be configured to generate a layer toolpath to control the 3D printing of the physical layer, including by partitioning the slice into zones and determining a zone order, based on a heat-aware criterion, for the layer toolpath to traverse for the 3D printing of the physical layer. The heat-aware toolpath engine may also be configured to provide the layer toolpath to support the 3D printing of the physical part.

Abstract: A system may include an access engine and a foam part generation engine. The access engine may be configured to access a computer-aided design (CAD) seat surface that represents a seat surface of a seat design and access seat parameters for the seat design. The foam part generation engine may be configured to construct a CAD foam part for the seat design based on the CAD seat surface and the seat parameters.

Abstract: A method is provided for transmission rate adaptation of one or more data units, the method including: receiving, by an adapter, the adapter including an adaptation circuitry, a plurality of data units according to a first transmission rate and at least one delay character separating two consecutive data units; and transmitting, by the adapter, each of the plurality of data units received according to a second transmission rate, wherein the second transmission rate is determined based on the at least one delay character received.

Abstract: A computing system may include a constraint learning engine and a constraint generation engine. The constraint learning engine may be configured to access a computer-aided design (CAD) assembly comprising multiple CAD parts and generate a representation graph of the CAD assembly, determine constraints in the CAD assembly, wherein the constraints limit a degree of movement between geometric faces of different CAD parts in the CAD assembly, insert constraint edges into the representation graph that represent the determined constraints; and provide the representation graph as training data to train a machine-learning model. The constraint generation engine may be configured to generate constraints for a different CAD assembly by applying the machine-learning model for the different CAD assembly.

Abstract: A computing system may include a metal stack tuning engine and a tuned metal stack application engine. The metal stack tuning engine may be configured to access an obscured metal stack definition specified for an integrated circuit (IC) manufacture process and tune selected metal stack parameters of the obscured metal stack definition to obtain a tuned metal stack definition. The metal stack tuning engine may do so by generating sampled metal stack definitions, constructing sampled layout geometries from the sampled metal stack definitions, computing parasitic capacitance value sets for the sampled layout geometries, and determining tuned values for the selected metal stack parameters through a curve fitting process. The tuned metal stack application engine may be configured to use the tuned metal stack definition to perform a parasitic capacitance extraction process for an input IC design.

Abstract: A circuit design in a hierarchical description is analyzed. The analysis comprises identifying electrical properties of circuit blocks in the circuit design. Circuit components of the circuit design are associated with geometric elements of a layout design. Then instances of each of the circuit blocks are classified into groups of instances based on the electrical properties. Rule checking is performed on one or more groups in the groups of instances for each of the circuit blocks by analyzing geometric elements associate with components of one instance for each of the one or more groups.

Abstract: A computing system may include an access engine and a toolpath reordering engine. The access engine may be configured to access an original layer toolpath for slice of a 3D CAD object as well as a heat criticality measure for the original layer toolpath. The heat criticality measure may specify a heat impact for different points on the multiple toolpath segments of the original layer toolpath for the 3D printing of the physical part using the original layer toolpath. The toolpath reordering engine may be configured to reorder the multiple toolpath segments into a modified layer toolpath, and the modified layer toolpath may have a heat criticality measure with a lesser heat impact on the physical part than the heat criticality measure for the original layer toolpath.

Abstract: A computing system may include an upgrade access engine configured to access a database upgrade to perform for a production database. The computing system may also include a database upgrade engine configured to generate multiple clones of the production database, including a production clone and a delta clone with instance data removed. The database upgrade engine may perform the database upgrade on the production clone, track changes to the production database, and push the tracked changes to the delta clone. After the database upgrade on the production clone completes, the database upgrade engine may perform the database upgrade on the delta clone, push upgraded data of the delta clone to the upgraded production clone, and set the upgraded production clone as an upgraded version of the production database.

Abstract: A computing system may include a hotspot processing engine and a hotspot prediction engine. The hotspot processing engine may be configured to access an input data set of hotspot locations on manufactured circuits of a circuit design, correlate the hotspot locations to layout data for the circuit design, and extract fragment feature vectors for the hotspot locations. The hotspot processing engine may further be configured to process the fragment feature vectors such that hotspot fragment feature vectors are a threshold percentage of the total number of feature vectors in the fragment feature vectors and provide the processed fragment feature vectors as a training set for training a machine-learning model. The hotspot prediction engine may be configured to apply the machine-learning model to characterize locations of the circuit design as a hotspot location or a non-hotspot location.

Abstract: A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.