Abstract: Methods and apparatus for pattern matching and classification are disclosed. In one example of the disclosed technology, a method of performing pattern matching according to a puzzle-matching the methodology includes analyzing an original source layout pattern and determining a signature for the original source layout pattern. A target layout is scanned to search for one or more portions of the target layout that have a signature that matches or is similar to the signature of the original source pattern. Similar patterns are searched based on a signature comparison of the source pattern and the target layout. In some examples of the disclosed technology, it is possible to match partial context to the original source pattern. In some examples, matches can be made in the target layout for different orientations of layout.

Abstract: This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.

Abstract: A computing system may include a hyperspace generation engine and a hyperspace processing engine. The hyperspace generation engine may be configured to access a feature vector set, and feature vectors in the feature vector set may represent values for multiple parameters of data points in a dataset. The hyperspace generation engine may further be configured to perform a principal component analysis on the feature vector set and quantize the principal component space into a hyperspace comprised of hyperboxes. The hyperspace processing engine may be configured to process the dataset according to a mapping of the feature vector set into the hyperboxes of the hyperspace.

Abstract: A computing system may include a virtual cross metrology engine configured to construct a given virtual metrology model. The given virtual metrology model may take, as inputs, process parameters applied for the given step of a semiconductor fabrication process. The virtual cross metrology engine may also be configured to construct a subsequent virtual metrology model, and the subsequent step is performed after the given step in the semiconductor fabrication process. Doing so may include determining inputs for the subsequent virtual metrology model from a combination of the process parameters applied for the given step of the semiconductor fabrication process, process parameters applied for the subsequent step of the semiconductor fabrication process, and a wafer value for the given step of the semiconductor fabrication process that the given virtual metrology model is configured to predict.

Abstract: A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Abstract: A computer-aided design (CAD) system may support spatially-aware detection of trapped support areas in 3D printing. The CAD system may detect trapped support areas in the surface mesh in that detected trapped support area do not have linear access to an opening in the surface mesh, including by surrounding the surface mesh with a virtual bounding box that encloses the surface mesh, mapping the virtual bounding box and surface mesh into a 3D cube space, and tracking mesh cubes and bounding cubes of the 3D cube space. For a given mesh face of the surface mesh, The CAD system may determine whether the given mesh face is part of a trapped support area by projecting a ray from the given mesh face and assessing the given mesh face as part of a trapped support area based on the ray passing through a mesh cube or a bounding cube.

Abstract: A single radio equipment test device includes a control unit for testing a plurality of antennas, (e.g., an antenna array). The control unit includes a first interface to operatively couple the control unit to an antenna under test, (e.g., arranged in a test chamber). The control unit further includes a second interface to operatively couple the control unit to a reference antenna, (e.g., also arranged in the test chamber). The control unit is configured to control and/or monitor the antenna under test and the reference antenna.

Abstract: A system may support augmented reality (AR)-based layup of plies to form a composite laminate. The system may include an AR headset configured to drive an AR view that digitally visualizes ply placement data on a composite part layup tool physically visible through the AR headset. The system may also include an AR ply layup engine AR ply layup engine configured to analyze a view of the AR headset to identify the composite part layup tool, obtain ply placement data, and provide ply placement data to the AR headset to digitally overlay on the composite part layup tool physically visible through the AR headset.

Abstract: A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.

Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

Abstract: A computer-implemented method is provided for determining a cut pattern of a lathe. The lathe is numerically controlled by a control device and includes a tool with a cutter acting on a workpiece. The workpiece has a start contour and a target contour to be achieved by cutting the workpiece according to the cut pattern. The method includes determining a path of a n-th layer of the cut pattern, wherein the n-th layer includes: for n?2: an infeed path linear and/or parallel to the target contour; a circular infeed path starting tangent to the target contour; an intermediate path linear and/or parallel to the target contour; a circular outfeed path ending tangent to the target contour; and for n?2: a smoothing path linear and/or parallel to the target contour.

Abstract: Systems and methods for process design and analysis of processes that result in products or analytical information are provided. A hypergraph data store is maintained and comprises versions of each process. A version comprises a hypergraph with nodes, for stages of the process, and edges. Stages have parameterized resource inputs associated with stage input properties, and input specification limits. Stages have resource outputs with output properties and output specification limits. Edges link the outputs of nodes to the inputs of other nodes. A run data store is maintained with a plurality of process runs, each run identifying a process version, values for the inputs of nodes in the corresponding hypergraph, their input properties, resource outputs of the nodes, and obtained values of output properties of the resource outputs.

Abstract: A circuit comprises a plurality of clock control devices. Each of the clock control devices is configured to generate a scan test clock signal for a particular clock domain in the circuit and comprises circuitry configured to select clock pulses of a fast clock signal as scan capture clock pulses for the particular clock domain based on a particular clock pulse of a slow clock signal and a scan enable signal. The order and spacing between the groups of the scan capture clock pulses for different clock domains correspond to the order and spacing of the clock pulses of the slow clock signal.

Abstract: Systems and methods may support build direction-based partitioning for construction of a physical object through additive manufacturing. In some implementations, a system may access a surface mesh representative of a 3D object and an initial build direction for construction of the object using additive manufacturing. The system may partition the surface mesh into an initial buildable segment and a non-buildable segment based on the initial build direction. The system may iteratively determine subsequent build directions and partition off subsequent buildable segments from the unbuildable segment until no portion of the non-buildable segment remains. The determined buildable segments and correlated build directions may be provided to a multi-axis 3D printer for construction of the represented 3D object through additive manufacturing.

Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

Abstract: Systems and methods to semantically compare product configuration models. A method includes receiving a first configuration model and a second configuration model. The method includes generating a first order logic (FOL) representation of the first configuration model and an FOL representation of the second configuration model. The method includes performing a satisfiability modulo theories (SMT) solve for nonequivalence satisfiability on the FOL representation of the first configuration model and the FOL representation of the second configuration model. The method includes storing an indication that the first configuration model is equivalent to the second configuration model when the SMT solve for nonequivalence satisfiability is not satisfied.

Abstract: A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

Abstract: This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes.

Abstract: Methods for modeling of parts with lattice structures and corresponding systems and computer-readable mediums. A method includes receiving a model of an object to be manufactured. The method includes receiving a user specification of a void region within the model to create a lattice. The method includes performing a trimming operation to create a trimmed lattice by tessellating void surfaces and grouping together at least one row of connected rods to be treated as a single entity.