Abstract: A portable traffic signal system with multiple signal heads where a substantially horizontal telescopic arm is used to support multiple signal heads, where each additional remote stage is initially inclined with respect to an adjacent less remote stage and multiple traffic signal control boxes are held to a trailer using a “J” hook and a hole in a trailer floor, in combination with a hand crank jack.

Abstract: Systems and methods are provided for object identifier translation using a key pairs platform in a virtualized or cloud-based computing system. A key pair refers to a pair of identifiers held by an entity. Each key pair includes at least one anonymized object identifier. Advantageously, the key pair system protects privacy and provides anonymity for objects by not disclosing the identity of the objects or the underlying data associated with the objects.

Abstract: A traffic radar system comprises a first radar transceiver, a second radar transceiver, a speed determining element, and a processing element. The first radar transceiver transmits and receives radar beams and generates a first electronic signal corresponding to the received radar beam. The second radar transceiver transmits and receives radar beams and generates a second electronic signal corresponding to the received radar beam. The speed determining element determines and outputs a speed of the patrol vehicle. The processing element is configured to receive a plurality of digital data samples derived from the first or second electronic signals, receive the speed of the patrol vehicle, process the digital data samples to determine a relative speed of at least one target vehicle in the front zone or the rear zone, and convert the relative speed of the target vehicle to an absolute speed using the speed of the patrol vehicle.

Abstract: A traffic radar system comprises a first radar transceiver, a second radar transceiver, a speed determining element, and a processing element. The first radar transceiver transmits and receives radar beams and generates a first electronic signal corresponding to the received radar beam. The second radar transceiver transmits and receives radar beams and generates a second electronic signal corresponding to the received radar beam. The speed determining element determines and outputs a speed of the patrol vehicle. The processing element is configured to receive a plurality of digital data samples derived from the first or second electronic signals, receive the speed of the patrol vehicle, process the digital data samples to determine a relative speed of at least one target vehicle in the front zone or the rear zone, and convert the relative speed of the target vehicle to an absolute speed using the speed of the patrol vehicle.

Abstract: A traffic radar system comprises a first radar transceiver, a second radar transceiver, a speed determining element, and a processing element. The first radar transceiver transmits and receives radar beams and generates a first electronic signal corresponding to the received radar beam. The second radar transceiver transmits and receives radar beams and generates a second electronic signal corresponding to the received radar beam. The speed determining element determines and outputs a speed of the patrol vehicle. The processing element is configured to receive a plurality of digital data samples derived from the first or second electronic signals, receive the speed of the patrol vehicle, process the digital data samples to determine a relative speed of at least one target vehicle in the front zone or the rear zone, and convert the relative speed of the target vehicle to an absolute speed using the speed of the patrol vehicle.

Abstract: An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3 × 3 × 64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.

Abstract: Disclose herein are embodiments related to a system made up of a lighting fixture and a radio frequency detection device. The lighting fixture having a secure housing and at least one power connection, and the radio frequency detection device being designed to operatively connect to the at least one power connection device within the lighting fixture.

Abstract: A traffic radar system comprises a first radar transceiver, a second radar transceiver, a speed determining element, and a processing element. The first radar transceiver transmits and receives radar beams and generates a first electronic signal corresponding to the received radar beam. The second radar transceiver transmits and receives radar beams and generates a second electronic signal corresponding to the received radar beam. The speed determining element determines and outputs a speed of the patrol vehicle. The processing element is configured to receive a plurality of digital data samples derived from the first or second electronic signals, receive the speed of the patrol vehicle, process the digital data samples to determine a relative speed of at least one target vehicle in the front zone or the rear zone, and convert the relative speed of the target vehicle to an absolute speed using the speed of the patrol vehicle.

Abstract: An unenrolled lightweight node is on a decentralized network with a trusted node and a plurality of peers. The unenrolled lightweight node and the peers run a lightweight blockchain consensus algorithm. The unenrolled lightweight node includes (a) circuitry for storing a token that includes a signature that includes at least a signature of at least a first identifier signed with a private key of the trusted node, the first identifier being associated with a public key of the unenrolled lightweight node, and (b) circuitry for broadcasting a request for blockchain enrollment of the unenrolled lightweight node to the plurality of peers. The authentication request including at least a second identifier that is associated with at least a public key of the unenrolled lightweight node, a signature created with at least the second identifier and a corresponding private key of the unenrolled lightweight node, and the token.

Abstract: A lightweight node in a decentralized network includes stores a blockchain with a plurality of blocks. The lightweight node adds blocks to the blockchain successively. A given block having a header and a body. The header includes a data merkle root generated as a root hash of a data merkle tree with one or more leaf nodes that are one or more hashes. A given hash being a hash of a combination of (1) a public key associated with a lightweight node of the decentralized network and (2) of a validity value associated with the public key indicating whether the public key is a valid public key. The data merkle root being insufficient for restoring the data merkle tree. But with a public key and an intermediate hash the date merkle root is sufficient for at least partly verifying the public key.

Abstract: A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which outputs a signed integer form fraction and a maximum exponent. A range estimator forms a possible range of values from the exponent differences and determines an adder precision. The integer form fractions are summed using the adder precision, a sign bit is extracted, and a floating point value is output. Each MAC processor provides its integer form fraction with a precision determined by the MAC processor's exponent difference.

Abstract: A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which output a signed integer form fraction with a first bitwidth and a second bitwith, along with a maximum exponent. The first bitwidth signed integer form fractions are summed by an adder tree using the first bitwidth to form a first sum, and when an excess leading 0 condition is detected, a second adder tree operative on the second bitwidth integer form fractions forms a second sum. The first sum or second sum, along with the maximum exponent, is converted into floating point result.

Abstract: A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates an integer form fraction accompanied by a sign bit and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. A range estimating process determines a possible range of values from the exponent differences and determines an adder precision. A summing process adds all of the integer form fractions using the determined adder precision, and converts the sum to a floating point value using the maximum exponent sum, sign bit of the summed integer form fractions, and optionally performs a 2's complement of the summed integer form fraction if the sign bit is negative.

Abstract: A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates: an integer form fraction at a first bitwidth and a second bitwidth greater than the first bitwidth, a sign bit, and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. The integer form fractions of the first bitwidths are provided to an adder tree using the first bitwidth, and if the sum has an excess percentage of leading 0s, then the second bitwidth is used by an adder tree using the second bitwidth to form a great precision integer form fraction. The sign, integer form fraction, and maximum exponent are provided to an normalizer which generates a floating point result.

Abstract: An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

Abstract: A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values. The Gain Balanced AMAC has a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. In each of a series of multiply-accumulate cycles, the X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

Abstract: A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.

Abstract: A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

Abstract: A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.

Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.