Abstract: A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.

Abstract: An adder device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A set of regions are positioned on a top layer above a continuous bottom layer, and the regions excited with magnetization for A and not A, B and not B, and C and not C to form a sum and an inverse carry output magnetization.

Abstract: Systems and methods are provided for electronic stimulus evaluation through one or more signals. The one or more signals protect underlying raw data relating to behavior, including purchase behavior and location-based behavior. A server platform in network communication with at least one signal buyer computer and at least one signal provider computer facilitates creation of the one or more signals. Anonymized identifiers are used to identify objects or consumers associated with behavior data and exposure to the electronic stimulus. The server platform provides optimization analytics for the stimulus based on the one or more signals, which include measurement signals, behavior signals, and lift signals.

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

Abstract: An AND or OR logic device has multiple layers of ferromagnetic material separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. The anti-magnetic response in a layer below a layer magnetized with a polarity is summed in a region which is coupled to an output, the output generating at least one of a AND or OR logic function on applied input magnetization.

Abstract: A dot product multiplier for matrix operations for an A matrix of order 1×m with a coefficient B matrix of order m×m. Processing Elements (PEs) are arranged in an m×m array, the columns of the array summed to provide a dot product result. Each of the PEs contains a sign determiner and a plurality of analog multiplier cells, one multiplier cell for each value bit. The multipliers operate over four clock cycles, initializing a capacitor charge according to sign on a first clock phase, sharing charge on a second phase, canceling charge on a third phase, and outputting the resultant charge on a fourth phase, the resultant charge on each column representing the dot product for that column.

Abstract: A traffic radar system comprises a first radar transceiver, a second radar transceiver, a speed determining element, and a processing element. The first radar transceiver transmits and receives radar beams and generates a first electronic signal corresponding to the received radar beam. The second radar transceiver transmits and receives radar beams and generates a second electronic signal corresponding to the received radar beam. The speed determining element determines and outputs a speed of the patrol vehicle. The processing element is configured to receive a plurality of digital data samples derived from the first or second electronic signals, receive the speed of the patrol vehicle, process the digital data samples to determine a relative speed of at least one target vehicle in the front zone or the rear zone, and convert the relative speed of the target vehicle to an absolute speed using the speed of the patrol vehicle.

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

Abstract: An NAND or NOR logic device has multiple layers of ferromagnetic material separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. The anti-magnetic response in a layer below a layer magnetized with a polarity is summed in a region which is coupled to an output, the output generating at least one of a NAND, or NOR logic function on applied input magnetization.

Abstract: A method, system, and apparatus are provided for a traffic enforcement system. A certification period can be stored and displayed and the device deactivated upon expiration thereof.

Abstract: A traffic radar system comprises a first radar transceiver, a second radar transceiver, a speed determining element, and a processing element. The first radar transceiver transmits and receives radar beams and generates a first electronic signal corresponding to the received radar beam. The second radar transceiver transmits and receives radar beams and generates a second electronic signal corresponding to the received radar beam. The speed determining element determines and outputs a speed of the patrol vehicle. The processing element is configured to receive a plurality of digital data samples derived from the first or second electronic signals, receive the speed of the patrol vehicle, process the digital data samples to determine a relative speed of at least one target vehicle in the front zone or the rear zone, and convert the relative speed of the target vehicle to an absolute speed using the speed of the patrol vehicle.

Abstract: A body-worn surveillance system is associated with the ICV system via a docking mechanism that is connected to the ICV system via a cable, or other means. The ICV system recognizes the specific body-worn system(s). In order to reduce power draw on the mobile battery powered BWV device and thus extend record time(s), the BWV wireless radio is left in a suspended or sleep state and the lower power draw Bluetooth radio is enabled. When the body-worn system is within a specified proximity (RSSI) of the ICV system's wireless Bluetooth transceiver and there are recorded files available for transfer, the BWV device's wireless Ethernet connection will be enabled to transfer AV files to the ICV system, which will then store those files on the ICV system's internal media.

Abstract: Systems and methods are provided for object identifier translation using a key pairs platform in a virtualized or cloud-based computing system. A key pair refers to a pair of identifiers held by an entity. Each key pair includes at least one anonymized object identifier. Advantageously, the key pair system protects privacy and provides anonymity for objects by not disclosing the identity of the objects or the underlying data associated with the objects.

Abstract: A method, system, and apparatus are provided for capturing a video image and speed of a target vehicle. A ranging device detects a distance to a target vehicle. The focal distance or zoom of a video camera is set and adjusted based on the distance. The speed of travel of the vehicle is detected, displayed, and/or stored in association with a video image captured of the vehicle by the video camera. A range of distances within which to capture the video image and speed of the vehicle may be set by detecting distances between a pair of landmarks or using GPS and compass heading data. An inclinometer is provided to aid initiation of a power-conservation mode. A target tracking time may be determined and compared to a minimum tracking time period. A device certification period can be stored and displayed and the device deactivated upon expiration thereof.

Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

Abstract: A code decompression engine reads compressed code from a memory containing a series of code parts and a dictionary part. The code parts each have a bit indicating compressed or uncompressed. When the code part is compressed, it has a value indicating the number of segments, followed by the segments, followed by an index into the dictionary part. The decompressed instruction is the dictionary value specified by the index, which is modified by the segments. Each segment describes the modification to the dictionary part specified by the index by a mask type, a mask offset, and a mask.

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

Abstract: Systems and methods are provided for object discovery and object mapping through an application with a Graphical User Interface (GUI). Objects are discovered through an object recommendation channel and through user input of key words and/or key phrases. Each object includes an Intensity of Interest (IoI), which is a relative preference for an object reflected by relative size in the object map. Additionally, the object map provides a visual display which indicates relationships among objects.

Abstract: A low power device has a Bluetooth connection and a WLAN interface that can be enabled for high speed communication. The low power device is coupled to an application program running on a remote computer such as a tablet over Bluetooth. When a large amount of data is requested, the high speed WLAN interface is enabled as an Access Point (AP) and data transmitted or received over the low power device AP WLAN interface until the block of data is transferred, after which the WLAN connection is torn down, and the WLAN interface disabled. In this manner, the power consumption during high speed data transfers is minimized.