Patents Assigned to Signals, Inc.
  • Publication number: 20220383002
    Abstract: A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.
    Type: Application
    Filed: May 31, 2021
    Publication date: December 1, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
  • Publication number: 20220382515
    Abstract: A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.
    Type: Application
    Filed: May 31, 2021
    Publication date: December 1, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
  • Publication number: 20220385566
    Abstract: A node mesh contains an originating node coupled to one or more nodes, each node having an communications interface input and a communications interface output. Each node has a route table with an association between a header amplitude and an output interface, such that a header having a particular amplitude causes the input node which received the message to couple the message to an associated communications interface output of the node. When the originating node outputs a message with a header amplitude, each node of the node mesh in turn directs the message to an output interface as directed by the node local route table to a terminating node of the node mesh, where the terminating node may be a training processor or inference processor for machine learning applications.
    Type: Application
    Filed: May 29, 2021
    Publication date: December 1, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Robert WISER, Venkat MATTELA, Wei XIONG
  • Publication number: 20220334797
    Abstract: A multiplier is formed from a plurality of nanomagnetic structures including slant edge input nanomagnetic structures, diagonal elongate interconnect nanomagnetic structures, and output nanomagnetic structures. Input logic levels are provided by inserting a magnetic field, which generates an set of output magnetic fields representing the product of the binary input values.
    Type: Application
    Filed: April 20, 2021
    Publication date: October 20, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Santhosh SIVASUBRAMANI, Sanghamitra DEBROY
  • Publication number: 20220336729
    Abstract: A multiplier device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A plurality of regions on a top surface are activated with a magnetic field in a first direction for a 1 value and in an opposite direction for a 0 value, the multiplication result presented as magnetic field direction on a plurality of output ferromagnetic regions.
    Type: Application
    Filed: April 19, 2021
    Publication date: October 20, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Venkat MATTELA, Sanghamitra DEBROY, Santhosh SIVASUBRAMANI
  • Publication number: 20220317316
    Abstract: A traffic radar system comprises a first radar transceiver, a second radar transceiver, a speed determining element, and a processing element. The first radar transceiver transmits and receives radar beams and generates a first electronic signal corresponding to the received radar beam. The second radar transceiver transmits and receives radar beams and generates a second electronic signal corresponding to the received radar beam. The speed determining element determines and outputs a speed of the patrol vehicle. The processing element is configured to receive a plurality of digital data samples derived from the first or second electronic signals, receive the speed of the patrol vehicle, process the digital data samples to determine a relative speed of at least one target vehicle in the front zone or the rear zone, and convert the relative speed of the target vehicle to an absolute speed using the speed of the patrol vehicle.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Applicant: Kustom Signals, Inc.
    Inventors: Maurice Shelton, Roger Adwell
  • Publication number: 20220308888
    Abstract: Embodiments are provided for reduction of lost cycles after branch misprediction in multi-thread microprocessors. In some embodiments, a method includes fetching, by first stage circuitry of a multi-thread microprocessor, a pair of consecutive instructions of a program executed in a thread. The method also includes determining, by second stage circuitry of said microprocessor, during a clock cycle, that a first instruction in the pair is a branch instruction. The method further includes fetching, by the first stage circuitry, during a second clock cycle, a pair of branch target instructions of the program using a branch prediction, and determining, by third stage circuitry of said microprocessor, during the second clock cycle, that the branch prediction is a misprediction. The method still includes sending the second instruction to the second stage circuitry during a third clock cycle, and decoding the second instruction by the second stage circuitry during the third clock cycle.
    Type: Application
    Filed: March 27, 2021
    Publication date: September 29, 2022
    Applicant: Redpine Signals, Inc.
    Inventor: Heonchul PARK
  • Publication number: 20220308889
    Abstract: A superscalar processor has a thread mode of operation for supporting multiple instruction execution threads which are full data path wide instructions, and a micro-thread mode of operation where each thread supports two micro-threads which independently execute instructions. An executed instruction sets a micro-thread mode and an executed instruction sets the thread mode.
    Type: Application
    Filed: March 27, 2021
    Publication date: September 29, 2022
    Applicant: Redpine Signals, Inc.
    Inventor: Heonchul PARK
  • Publication number: 20220308887
    Abstract: Embodiments are provided for mitigation of branch misprediction penalty in hardware multi-thread microprocessors. In some embodiments, a hardware multi-thread microprocessor includes first stage circuitry that fetches a pair of consecutive instructions of a program executed in a thread. Such microprocessor also includes second stage circuitry that determines, during a clock cycle, that a first instruction in that pair is a branch instruction. The first stage circuitry fetches, during a second clock cycle after the clock cycle, a pair of branch target instructions of the program using a branch prediction. Such microprocessor further includes third stage circuitry that determines that the branch prediction is a misprediction during the second clock cycle. The first stage circuitry sends the second instruction to the second stage circuitry during a third clock cycle after the second clock cycle. The second stage circuitry decodes the second instruction during the third clock cycle.
    Type: Application
    Filed: March 27, 2021
    Publication date: September 29, 2022
    Applicant: Redpine Signals, Inc.
    Inventor: Heonchul PARK
  • Publication number: 20220269485
    Abstract: A process for performing vector dot products receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The process generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits to form a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information including MAX_EXP and EXP_DIFF. A second pipeline stage receives the multiplied pairs of normalized mantissas, optionally performs an exponent adjustment, pads, complements and shifts the normalized mantissas, and the results are added in a series of stages until a single addition result remains, which is normalized using MAX_EXP to form the floating point output result.
    Type: Application
    Filed: February 21, 2021
    Publication date: August 25, 2022
    Applicant: Redpine Signals, Inc.
    Inventor: Dylan FINCH
  • Publication number: 20220269753
    Abstract: A vector dot product multiplier receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The dot product multiplier generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits in a few pipelined stages. A first pipeline stage generates a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information. A second pipeline stage receives the multiplied pairs of normalized mantissas, performs an adjustment, performs a padding, complement, and shift, and sums the results in an adder stage. The resulting integer is normalized to generate a sign bit, exponent, and mantissa of the floating point result.
    Type: Application
    Filed: February 21, 2021
    Publication date: August 25, 2022
    Applicant: Redpine Signals, Inc.
    Inventor: Dylan FINCH
  • Publication number: 20220244913
    Abstract: A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.
    Type: Application
    Filed: January 31, 2021
    Publication date: August 4, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin KRAEMER, Ryan BOESCH, Wei Xiong
  • Publication number: 20220247422
    Abstract: An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 4, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
  • Publication number: 20220244914
    Abstract: A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.
    Type: Application
    Filed: January 31, 2021
    Publication date: August 4, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
  • Publication number: 20220244915
    Abstract: A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 4, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
  • Publication number: 20220247425
    Abstract: An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
    Type: Application
    Filed: January 31, 2021
    Publication date: August 4, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin Kraemer, Ryan BOESCH, Wei XIONG
  • Publication number: 20220206755
    Abstract: A differential multiplier-accumulator accepts A and B digital inputs plus a sign bit and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. One of the positive and negative unit element is enabled by the sign bit, the enabled unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element, which charge to charge transfer lines, and the charge transfer lines are coupled to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG
  • Publication number: 20220206753
    Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Ryan BOESCH, Martin KRAEMER, Wei XIONG
  • Publication number: 20220207247
    Abstract: A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Ryan BOESCH, Martin KRAEMER, Wei XIONG
  • Publication number: 20220206754
    Abstract: A plurality of unit elements share a charge transfer bus, each unit element accepts A and B digital inputs and generates a product P as an analog charge transferred to the charge transfer bus, each unit element comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates of each unit element are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges contributed by all unit elements to the charge transfer lines according to a bit weight and converted to a digital value output.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Applicant: Redpine Signals, Inc.
    Inventors: Martin KRAEMER, Ryan BOESCH, Wei XIONG