Abstract: A tape ball grid array (TBGA) semiconductor package having a one metal layer interconnect substrate is provided. Further provided is a method for making the TBGA package having electrical connection through the one metal layer interconnect substrate down to a ground plane. The method includes: (a) defining at least one via hole through the one metal layer interconnect substrate; (b) filling the at least one via hole of the one metal layer interconnect substrate with a first solder ball; (c) reflowing the first solder ball; (d) placing a second solder ball over the reflowed first solder ball; and (e) reflowing the second solder ball to attach the second solder ball to the reflowed first solder ball. The reflowed first solder ball and the reflowed second solder ball form a ground via connection to the ground plane of the TBGA.

Abstract: Disclosed is a semiconductor package arrangement. The package arrangement includes a heat spreader for dissipating heat generated within the semiconductor package arrangement. The package further includes a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive. The ground plane has a first aperture defining a path to a surface of the heat spreader that is configured to receive a semiconductor die. An interconnect substrate is adhesively attached to the ground plane, and the interconnect substrate has a complementary second aperture over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package arrangement.

Abstract: Disclosed is a semiconductor package arrangement. The package arrangement includes a heat spreader for dissipating heat generated within the semiconductor package arrangement. The package further includes a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive. The ground plane has a first aperture defining a path to a surface of the heat spreader that is configured to receive a semiconductor die. An interconnect substrate is adhesively attached to the ground plane, and the interconnect substrate has a complementary second aperture over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package arrangement.

Abstract: In a virtual memory system, a guarded region allows access to protected code and data without intervention from a processor's operating system by redefining regions of an address space with reference to gates indicating points of entry for those regions. A non-hierarchial access path in the form of a tree-like structure permits a process to access resources and data while controlling access thereto and return therefrom.

Abstract: A linear transconductance amplifier includes a differential transconductance amplifier stage and a differential correction amplifier stage. In order to achieve linear operation over a wide dynamic range, the nonlinearities generated in the transconductance amplifier stage are substantially cancelled by the nonlinearities generated in the correction amplifier stage. This is accomplished by cross-coupling the two stages and establishing the relative gain of the correction amplifier stage with respect to the transconductance amplifier stage such that the desired cancellation occurs. In a preferred embodiment, optimum cancellation occurs when the gain of the correction amplifier stage is substantially one-half the gain of the transconductance amplifier stage.

Abstract: A low resistance closed feedback loop regulated current source for supplying a load, the source being of the type including a transistor having input and output electrodes respectively connected between voltage input and current output terminals, and said transistor having a control electrode. The feedback loop includes amplifying means having an output connected to the transistor control electrode and having first and second inputs providing differential current gain for signal current at said inputs and for maintaining minimum differential voltage between said inputs. First and second PN semiconductor structures having first and second electrodes and having dissimilar junction boundary areas are provided with the first electrodes of said structures being connected to the respective first and second inputs of the amplifying means. A resistor is provided connected between the second electrode of the structure having the greater boundary area and the second electrode of the remaining structure.