Abstract: A protection device (14) for an integrated circuit (12) created on a semiconductor body (24 and 26) utilizes one or more semiconductor diodes (D.sub.L and/or D.sub.H) that have subsurface PN junctions (46 and/or 56) for preventing high-magnitude voltages, such as those generated by electrostatic discharge, from damaging sensitive electronic elements of a protected circuit component (16) formed from part of the body. The device is fabricated by an epitaxial layer/double buried region process.

Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22 and 24) fully adjoining a recessed oxide insulating region (16). The PN junction (30) of the upper diode of each pair lies in non-monocrystalline semiconductor material. A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and a buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency as well as provide intermediate electrical connections.

Abstract: Planarized insulating layers provided with planarized contacts are formed on semiconductor devices by forming vias through an insulating layer having a generally planar exposed surface, depositing a layer of a conductive layer on this upper surface of the insulating layer in an amount at least sufficient to at least partially fill all of the vias, depositing a planarized layer on the exposed surface of the conductive layer and then etching away the planarized layer and the conductive layer by use of an etchant that removes the planarized layer and the conductive layer at substantially the same rate, until the generally planar upper surface of the insulating layer is exposed.

Abstract: A field-programmable logic architecture is centered on a single array of programmable gates that perform either logical NAND or logical NOR operations. Foldback loops can be readily programmed through the array to enable the user to achieve different numbers of logic levels.

Abstract: A semiconductor PROM containing a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16) is fabricated by a process in which the insulating region serves as a mask to control the lateral extents of the dopants utilized to define the diodes. The intermediate cell regions are ion implanted to obtain maximum dopant concentration near their mid-points. This facilitates programming operation.

Abstract: During the deposition of a metallic layer on an N-type semiconductive region to form a Schottky diode in a structure placed in a highly evacuated chamber, at least one selected gas is introduced into the chamber to control the forward voltage across the diode.

Abstract: A circuit for processing the control signal inputs for a control data signal decoder wherein a reference voltage and a reference current are generated for use in processing a stream of control signal bits. The control signal data stream is filtered, buffered and exponentialed. The processing serves to cancel out variations in temperature, resistance, process variations and circuit voltages to yield a stable control signal current.

Abstract: A circuit capable of simulating a transistor or a semiconductor diode with controllably adjusted voltage characteristics contains a main transistor (Q0). An input voltage (V.sub.CS) to a control system (8) is amplified with a gain set by a pair of resistors (R1 and R2) to produce a control voltage (V.sub.C) for the transistor. This downscales the forward voltage characteristics of the circuit from those of the transistor. A floating power supply (10) in series with the control electrode of the transistor permits upscaling or further downscaling of the circuit voltage range.

Abstract: In a virtual memory system, a guarded region allows access to protected code and data without intervention from a processor's operating system by redefining regions of an address space with reference to gates indicating points of entry for those regions. A non-hierarchial access path in the form of a tree-like structure permits a process to access resources and data while controlling access thereto and return therefrom.

Abstract: A circuit switches with a hysteresis defined by separately controllable thresholds which can be made largely independent of temperature and fabrication conditions. The circuit contains a pair of differential portions (21 and 22) and an arithmetic component (24). The hysteresis is introduced into the circuit by using positive feedback to control the position of a switch (23) in such a manner as to change the transconductance of the circuit as it is switching.

Abstract: A pair of complementary logic gates (A and B) are used to test for faults in a group of electronic components (C1-C3) which provide respective component signals (S1-S3) indicative of their condition. One (A) of the gates ideally generates the logical OR or NOR of the component signals. The other (B) ideally generates their logical AND or NAND. The test procedure involves providing the components with information patterns that would ideally cause all the component signals to go to a logical "0" in one step and to logical "1" in another step. The actual values of the gate output signals (OA and OB) during these two steps are then compared with the respective ideal values to assess the condition of the components.

Abstract: The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access controller comprises a cache controller and a translation unit which are connected in parallel to an address bus connected to the processor and by which virtual addresses are transported. The memory access controller supports segments which are unit of sharing the memory, each segment is split up into pages. The memory access controller also supports regions which contain at least one segment. The memory access controller further supports sectors, divided into blocks which are other units of sharing the memory. And the memory access controller is also provided for enabling access with I/O units.

Abstract: A technique for producing planarized semiconductor surfaces and for isolating semiconductor islands.

Abstract: A method for fabricating insulated gate field effect transistors in NMOS or CMOS with source and drain regions having lightly doped extensions wherein the source and drain regions are made with a self-aligned process and a device made in accordance with such a method.

Abstract: An input portion (4, 6) of a differential amplifier circuit amplifies a differential input signal to produce an amplified signal between a pair of terminals. A summing section contains two complementary pairs of like-polarity amplifiers (13, 14 and 19, 20). Each has a first flow electrode, a second flow electrode, and a control electrode. A substantially constant bias voltage is supplied to the control electrodes of the first pair (13, 14) whose second electrodes are respectively coupled to the second electrodes of the second pair (19, 20). Their first electrodes are respectively coupled to the terminals and to corresponding impedance elements (11, 12). The control electrodes of the second pair are coupled together to receive a voltage dependent on the voltage at the second electrode of one (13) of the first pair so as to produce a representative output signal at the second electrode of the other (14) of the first pair.

Abstract: A multi-step A/D converter of the successive approximation type utilizes a single three-position switchable current-output DAC in combination with a voltage divider, a plurality of comparators, a decoder, a successive approximation register and a control logic module to provide a high speed, high resolution A/D converter requiring fewer parts than the prior art A/D converters of this general type.

Abstract: A NOR gate consisting of a set of input FET's (Q1.sub.1 -Q1.sub.M) has a clamp (12/ Q2) that, when at least one of the input FET's is turned on, clamps the logical low level of the gate output voltage at a value which is largely constant irrespective of how many of the input FET's are conductive.

Abstract: A ratioless, zero d.c. power dissipating FET programmable logic array including a column boost capacitor for maintaining the columns of selected AND array transistors at approximately their precharged voltage while their associated OR array transistors are being evaluated.

Abstract: A programmable status register arrangement which enables the status of a plurality of status registers in a system to be checked simultaneously including fusible links connected to the outputs of the status registers whereby a user of the arrangement can program it to control the transmission of status signals by the plurality of status registers.

Abstract: A flip-flop with a built-in enable function realized by the addition of two transistors between the trigger circuit and the output nodes of the flip-flop. This embodiment of the enable function causes no increase in power dissipation and may be used in any type of flip-flop.