Abstract: A portion (28) of photosensitive material is created by an underetching/shadowing technique in such a manner as to have an extremely narrow width.

Abstract: Circuit means for recorders in which the same external pin receives a play signal, a record signal, and a noise reduction signal generated by a user. The circuit means is comprised of a differentiating means for receiving the play and record signals and differentiating between them. A memory means is connected to the differentiating means and stores an indication of the last received of the signals. A first switch means is connected to the memory means and is operable to a first condition to control the play function when the memory means indicates the play signal was last received and to a second condition to control the record function when the memory means indicates the record signal was last received. A second switch means is connected to the external pin receiving the noise reduction signal and generating an ouptut signal to turn on noise reduction means during either the play or record mode.

Abstract: A steering circuit (10) in a differential amplifier having a pair of differentially arranged input amplifiers (A1 and A2) steers current from a pair of current sources (11 and 12) in such a way as to enhance slew rate without increasing offset voltage. The steering circuit is formed with a pair of steering amplifiers (A3 and A4) arranged in a differential configuration through a pair of resistors (R3 and R4).

Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.

Abstract: In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise the virgin state threshold voltage of the memory cell to a high positive value, such as 4 volts. Additionally, the overlap area between the control gate and the floating gate is reduced to the extent that the capacitance between the floating gate and the control gate is substantially equal to the capacitance between the floating gate and the substrate during programming, but the effective capacitance between the floating gate and the substrate is greatly reduced during erase mode. As a result, little or no tunneling occurs during programming and the threshold voltage level is the same as the virgin threshold value of the memory cell.

Abstract: An array arrangement for EEPROMS in which each memory cell has two transistors. Selection is simplified whereby in selecting a cell all of the cells in the selected row are connected to one terminal of the writing circuit and all the cells in the selected column are connected to the other terminal. This selection process prevents any cell from being written into except the cell at the intersection of the selected row and the selected column.

Abstract: A structure having substantial surface evenness is created by a method in which an insulating layer (24) that has an upward protrusion (26) is formed on a patterned conductive layer (20) having a corresponding upward protrusion (22). A further layer (28) having a generally planar surface is formed on the insulating layer. Using an etchant that attacks the further layer much more than the insulating layer, the further layer is etched to expose at least part of the insulating protrusion. The further layer and the insulating layer (as it becomes exposed) are then etched with an etchant that attacks both of them at rates not substantially different from each other. This brings the upper surface down without exposing the conductive layer, particularly its upward protrusion.

Abstract: A frequency detector receiving two input frequencies and generating a pump-up/pump-down signal for control of a phase locked loop by matching the frequency of a voltage controlled oscillator to the frequency. The lock is independent of the phase relationship of the signals.

Abstract: An absolute-value analog-to-digital converter containing a chain of matched main absolute-value differential amplifiers (A.sub.1 -A.sub.N) has a gain control for regulating the gain of each main amplifier utilizing an auxiliary absolute-value differential amplifier (A.sub.GC) matched to the main amplifiers. An offset control in the converter drives the offsets of the amplifiers toward zero by using a further absolute-value differential amplifier (A.sub.OC) matched to the other amplifiers. The gain and offset control are implemented with suitable feedback circuitry.

Abstract: A bipolar gate has an output transistor (Q5) that switches in response to the voltage at an emitter of a drive transistor (Q2 or Q10). An active pull-off circuit (14) discharges the base of the output transistor (Q5) when it turns off. The discharge path is provided through a pull-off transistor (Q7) whose collector is coupled to the base of the output transistor. The switching of the pull-off transistor is regulated with a control circuit containing a trigger circuit and a bias circuit. The trigger circuit is coupled between the bias circuit and a collector of the drive transistor. A "kicker" circuit formed with an input transistor (QC1) and a voltage reference (18) speeds up the switching of the drive transistor.

Abstract: A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circiut input signal (V.sub.IN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (V.sub.OUT) during hold. Switching circuitry (S1, S2, and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.

Abstract: A bipolar input circuit for regulating the current/voltage level at the base of a switching transistor (QA) provides a capacitively-controlled discharge path from the base through a discharge transistor (QC) when an input signal (V.sub.I) makes certain voltage transitions. The base of the switching transistor responds to the voltage at an emitter (E1) of an input transistor (QB) which has another emitter (E2) coupled to the base of the discharge transistor. Its base is further coupled to a capacitor (C) which controls the discharge path.

Abstract: In an improved method for growing an oxide layer on a silicon surface of a semiconductor body, the semiconductor body is first provided with a silicon surface. A first oxide layer portion is then grown over the silicon surface in a first thermal oxidation process at a temperature of less than about 1000.degree. C. The semiconductor device is then annealed in a nonoxidizing ambient at a temperature above about 1000.degree. C., and finally a second oxide layer portion is then grown over the first oxide layer portion in a second thermal oxidation process to complete the growth of the oxide layer. The silicon surface may be of either polycrystalline or monocrystalline material. This method avoids both the dopant outdiffusion problems associated with present high-temperature oxidation processes and the stress-related irregularities associated with known low-temperature oxidation processes.

Abstract: A sense amplifier with two input control stages whose input voltages are equalized during a precharge cycle by a switching means.

Abstract: A phase detector for use with a phase locked loop where the input has missing pulses. The detector processes two input frequencies and generates either a pump-up or a pump-down signal on separate outputs. The reference input may have missing transitions, as often happens in recovering the clock from encoded data. The phase detector comprises three bistable flip-flops and a gate interconnected to respond to the two input frequencies to produce either a pump-up pulse of variable width proportional to the phase difference between the pulses of the two input frequencies or a fixed width pump-down pulse.

Abstract: A device for testing continuity and current leakage at leads of an electronic circuit such as an integrated circuit has a contact structure (16) having test terminals (T1-T28) for contacting the leads. A first and a second of the leads are power supply leads respectively contactable with a first and a second of the test terminals (T14 and T28 or T26). Continuity/leakage detection is done with one or more corresponding detection circuits (D1-D28). Each detection circuit has a channel along which both continuity and leakage are tested. A supply switching circuit (26) appropriately switches voltages between values suitable for continuity testing and values suitable for leakage testing.

Abstract: A novel write circuit arrangement for an EEPROM type memory system operable in response to the difference between the information stored in each addressed cell and the information to the be stored therein during a writing cycle and writing information into only those addressed cells for which a difference exists regardless of whether the difference indicates to charge or discharge the cell. The arrangement also can simultaneously charge one cell of a byte while discharging another cell of the same byte.

Abstract: A bipolar signal translator contains a pair of transistors (Q1 and Q2) arranged as a current mirror with their emitters coupled to a voltage supply (V.sub.EE) by way of a pair of impedance elements (R4 and R5) that improve stability. Their collectors are coupled through another pair of impedance elements (R1 and R2) to an input transistor (Q4 or Q5) and to a device circuit (D1 and D2, D3 and D4, or Q4). The collector of one of the current-mirror transistors (Q2) is coupled to the base of an output transistor (Q3) whose collector is preferably coupled through an output impedance element (R3) to a current-control transistor (Q6) that improves power utilization.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.