Abstract: A glitchless terminal count indication digital counter having a clock signal as an input thereto is disclosed and comprises a state logic means comprised of a plurality of DQ flip-flops for providing a digital count with the clock signal being sent to an input thereof, a next state decode means, a next terminal count decode means for providing an indication at its output that the digital output count will reach a terminal count at the next clock cycle, and a terminal count logic means for obtaining the indication from the next terminal count decode means and providing therefrom at the next clock cycle a glitchless terminal count indication. The next state decode means has inputs and outputs, with the digital count being an input thereto, and the state logic means and the next terminal count decode means being coupled to the output thereof.

Abstract: The invention centers around a system for interpolating between multiple pairs of main complementary signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is done with two strings (12) of a selected number of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.NO -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. The interpolated signals are taken from other pairs of corresponding nodes along the strings. The interpolation system is particularly suitable for use in an analog-to-digital converter of the folding type.

Abstract: A voltage translator containing a bipolar transistor (Q1), a rectifier (10), a resistor (R1), and a first clamp (12) converts an input voltage (V.sub.I) into one or more output voltages of restricted voltage swing. The first clamp clamps the emitter voltage of the transistor when it is turned on. In one version, the translator includes a second clamp (14) that clamps the collector voltage of the translator when it is turned off. The translator then provides an output voltage (V.sub.O) inverse to the input voltage. In another version, the first clamp is connected between a voltage supply (V.sub.EE) and the emitter of the transistor. Its collector is connected directly to another voltage supply (V.sub.CC) so that the translator only makes non-inverting translations.

Abstract: A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.

Abstract: A Schottky-type diode has a conductor-to-semiconductor barrier height .phi..sub.B that is controlled by adjusting the thickness of a metal silicide layer (22) which forms a rectifying junction (20) with an N-type semiconductor (24). The silicide layer is constituted with two or more metals such as platinum and nickel.

Abstract: Various voltage and current sources which are substantially independent of the positive supply rail are provided, some of which are also temperature independent.

Abstract: A signal-conditioning circuit provides an output signal (V.sub.O) at a frequency representative of an effect such as strain or temperature that acts on a resistance bridge (20) preferably arranged in a Wheatstone configuration. A pair of energizing voltages (V.sub.E1 and V.sub.E2) are supplied on corresponding lines (21 and 22) to energize the bridge. The signal-conditioning circuit contains an integrator (34 and C1), a comparator that compares the integrator output voltage (V.sub.I) with one of the energizing voltages (V.sub.E2), and switching circuitry (23 and 24) that suitably switches the polarity of the energizing voltages in response to the output voltage.

Abstract: A non-inverting low power high speed bootstrapped buffer having a depletion mode FET device which senses a rising voltage triggers the bootstrap of a high capacitance node isolated from the input. Heavy output loading can be isolated from the bootstrap node. High resistance devices are used to make a fully static circuit.

Abstract: An MOS device having a planar configuration in which the top surfaces of the source, drain and gate electrodes are coplanar, and the overlying electrical contact structure is also planar, is produced by a method of fabrication in which the gate is defined by forming an oxide mesa on a substrate, building up the substrate with semiconductor material around the mesa, removing the mesa, and filling the resultant trough with doped polysilicon to form the self-aligned gate. Line width and alignment control are enchanced. The planarity of the device and the improved dimensional control enable a reduction of device dimensions and consequently increased device density in integrated circuits.

Abstract: Surface features of a semiconductor structure above a predetermined level are exposed for selective treatment (e.g., etching) by forming a layer of a solvent-expanded polymer on the surface of the structure, and allowing the layer to dry and cure, thereby relaxing to the predetermined level, at which it protects the underlying structure during treatment. Subsequently, the protective layer is removed by rinsing in a solvent.

Abstract: Gate sidewall spacers are created by a two-step procedure in fabricating a field-effect transistor using a protective material such as silicon nitride to prevent gate-electrode oxidation. In the first step, a layer (32) of insulating material is conformally deposited and then substantially removed except for small spacer portions (34) adjoining the sidewalls of a doped non-monocrystalline semiconductor layer (20A) destined to become the gate electrode (36). The second step consists of performing an oxidizing heat treatment to increase the thickness of the spacer portions. No significant gate dielectric encroachment occurs. Also, the spacers achieve a profile that substantially avoids electrical shorts.

Abstract: A device (16) for preventing an input signal (V.sub.I) applied to a terminal (12) of an integrated circuit from damaging a section (18) of the circuit contains a regular enhancement-mode insulated-gate FET (Q1 or Q2), a resistor (R1 or R2) that enables the regular FET to act temporarily like a "floating-gate" FET, and a thick-oxide insulated-gate FET (Q3).

Abstract: A field-programmable device contains a buffer (20) located between a pair of programmable circuits (14 and 16) along a column (10) connecting the circuits. The buffer provides increased current to the column portion connected to one of the circuits (16) without increasing the current supply requirements for the column portion connected to the other circuit (14). This permits the device to switch faster and/or to accommodate programmable circuits of large size. The buffer also enables the same select circuitry to be used in programming both circuits without causing a significant voltage between them during normal operation.

Abstract: In a bit-mapped display system, a logical subsystem for programmable sharing of access to a memory in a computer system among a plurality of system resources wherein various modes of operation are supported by the logic and are programmably selected by the user. The use of display memory is controlled between updating and display accesses to prevent breakup of the video image while said image is being changed.

Abstract: A select buffer circuit includes a first inverter circuit, a second inverter circuit connected to the first, and a circuit for charging and discharging the base of an inverter transistor in the second inverter circuit from a node in the first inverter circuit. The charging and discharging circuit includes a Schottky diode connected to the inverter transistor, a Schottky transistor connected in series with the diode, and a resistor for coupling the base of the Schottky transistor to the node in the first inverter circuit. A bipolar multiplexer including the select buffer circuit offers the advantage of an improved output waveform.

Abstract: A method for fabricating a semiconductor device in which the base resistance is minimized to increase the speed of operation of the device. This is accomplished because the device made by the method makes it possible to form the base and emitter contacts next to each other laterally but spaced vertically.

Abstract: A test device (40) has a patterned conductive layer (42 or 44) particularly adapted for use in an E-beam probe system (FIG. 3) to study how local electric fields influence probe voltage measurements. The layer is composed of two or more conductors (A and B.sub.J C and D.sub.J) separated from each other. Each conductor has a group of fingers. The fingers (F1.sub.p, F0.sub.p, F2, F0.sub.Q and F1.sub.Q) run parallel to one another and are at least partially interdigitated. The width of each finger is constant along its length. The widths of the fingers and the spacings between them vary from finger to finger according to a selected pattern.

Abstract: A switching device (22) responsive to an input voltage V.sub.A is powered by low and high internal supply voltages V.sub.L and V.sub.H. The device changes state as V.sub.A -V.sub.L passes a threshold voltage V.sub.T. After the device makes a desired change of state in response to rising V.sub.A, a hysteresis circuit (24) temporarily decreases V.sub.T below that which would otherwise be present. Likewise, after the device makes a desired change of state in the opposite direction when V.sub.A is falling, the hysteresis circuit temporarily decreases V.sub.T. In both cases, V.sub.T later automatically returns to its original value. This dynamic hysteresis prevents spikes in V.sub.L and V.sub.H from causing undesired changes in state.

Abstract: An on-chip regulated substrate bias voltage generator for an MOS integrated circuit includes a ring oscillator (10) for developing a true signal and its complement. The signals are applied to a charge pump (12) that includes two capacitors (C1 and C2) and a plurality of rectifiers (22, 24, and 26). The charge pump produces a substrate bias voltage (V.sub.BB) which is supplied to the gate of a depletion-mode field-effect transistor (28) whose source receives a reference voltage (V.sub.SS). The transistor forms part of a control circuit (14) coupled to the ring oscillator. In the N-channel case, the charge pumping action on the substrate drives the substrate bias negative until it reaches the sum of the reference voltage and threshold voltage of the depletion-mode transistor. This enables the control circuit to control the operation of the ring oscillator so as to regulate the substrate bias voltage.

Abstract: A double-ended code converter (10) contains three or more like-configured amplifiers (T.sub.O -T.sub.M+1). Each has a first flow electrode (E1), a second flow electrode (E2), and a control electrode (CE) for receiving a signal to control charge carriers moving from the first electrode to the second. The first electrodes are coupled to a circuit supply (12) which may be a current source or a voltage supply. The second electrodes are selectively coupled to one or the other of a pair of lines (L.sub.B and L.sub.BN) which are coupled to respective load elements (14.sub.B and 14.sub.BN) to provide a pair of complementary signals (V.sub.B and V.sub.BN).