Abstract: A system for approximating a least recently used (LRU) algorithm for memory replacement in a cache memory. In one system example, the cache memory comprises memory blocks allocated into sets of N memory blocks. The N memory blocks are allocated as M super-ways of N/M memory blocks where N is greater than M. An index identifies the set of N memory blocks. A super-way hit/replacement tracking state machine tracks hits and replacements to each super-way and maintains state corresponding to an order of hits and replacements for each super-way where the super-ways are ordered from the MRU to the LRU. Storage for the state bits is associated with each index entry where the state bits include code bits associated with a memory block to be replaced within a LRU super-way. LRU logic is coupled to the super-way hit/replacement tracking state machine to select an LRU super-way as a function of the super-way hit and replacement history.

Abstract: A system for repairing a memory column includes a multiplexer operable to receive a first data bit and a second data bit. The multiplexer is operable to select one of the first data bit and the second data bit. The system also includes a control generator operable to receive a control signal indicating an error in the first data bit. The control generator is operable to generate a select signal, and the multiplexer is operable to select the second data bit in response to the select signal.

Abstract: The present invention provides a system and method that facilitates data consistency maintenance between two segments of memory. A data consistency maintenance and recovery system and method of the present invention uses a dual page configuration and locking process to store and track data. A primary page is used as the primary data storage location and a mirror page operates as a copy of the primary page, except during certain stages of data manipulation operations. In one embodiment the present invention facilitates consistency maintenance during a write operation to a database. The present invention also facilitates data recovery following a system or process crash.

Abstract: A multiprocessor computer system includes a method and system of handling invalidation requests to a plurality of alias processors not sharing a line of memory in a computer system. A memory directory interface unit receives an invalidation request for a shared line of memory shared in a plurality of sharing processors. A superset of processors in the computer system that includes each of the sharing processors is determined that includes at least one alias processor not sharing the shared line of memory. An invalidation message is transmitted to each processor in the superset of processors. The number Na of alias processors in the superset of processors is determined and a superacknowledgement message is provided that is equivalent to acknowledging receipt of Na invalidation messages.

Abstract: A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned to jobs based on actual time a job spent in a queue requesting execution on a central processing unit (CPU) in the computer system between scheduler ticks and amounts of time jobs ran on the CPU between scheduler ticks. At the end of a time slice, a job is selected for execution on the processor based on earnings apportioned to each job.

Abstract: A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.

Abstract: In a computer system having a plurality of modules connected by a bus, wherein the plurality of modules includes a first module and wherein the system has a word width of two or more bytes, a system and method of byte swapping bytes within a word stored in a location on the first module. An address is constructed, wherein constructing an address includes inserting address bits pointing to the location and activating an attribute bit in the address indicating whether bytes within the word should be swapped. The address is driven on the bus and received at the first module. If the attribute bit is active, byte swapping the word.

Abstract: A cable connector assembly for high frequency applications having reduced electromagnetic emissions. Aspects include providing physical spacing and electrical isolation between the signal conductors and a conductive housing. An isolative member provides reduced capacitive coupling. One embodiment includes spring preloading of the electrical connecter relative to the housing. One embodiment includes a connector floating longitudinally within a conductive housing.

Abstract: A method, system, and program product for designing and verifying an electronic circuit. A circuit logic design is translated into a netlist using a synthesis tool. The synthesis tool receives inputs of placing, routing, and timing information. Timing delays in the logic design are represented in the netlist using the placing and routing information. It is determined whether a timing goal has been reached based on the timing delays. When the timing goal has not been reached, changes are made to the placing, routing, and timing information, and the synthesis tool is re-executed using the changed information until the timing goal is reached.

Abstract: A display is capable of displaying images in response to differently formatted signals. The display includes a switch that enables a user to select among a plurality of signal formats. The switch has a first setting that corresponds to a first of the plurality of signal formats and a second setting that corresponds to a second of the plurality of signal formats. The display also includes a memory module that receives requests from a channel and transmits a response associated with the setting of said switch.

Abstract: A system and method for generating a image, where the image comprises both a graphical user interface (GUI) and a subject graphics image. A first graphics pipeline renders the subject graphics image. A second graphics pipeline renders the GUI graphics data. A compositor then composites together the rendered subject graphics data that is produced by the first graphics pipeline, and the rendered GUI graphics data that is produced by the second graphics pipeline.

Abstract: A driver operable with two power supplies, and provides, among other things, a high data communication rate, stabilized operating parameters including voltage output high, voltage output low, and on resistance, and edge rate over a wide range of variations in manufacturing process, operating voltages and temperature.

Abstract: A modular computing system that includes an enclosure and a rack at least partially mounted within the enclosure. The modular computing system further includes a plurality of modular bricks that each include electronic components. The modular bricks are mounted in the rack and connected to the conduits in the rack. A fan is also connected to the conduits in the rack such that the rack exchanges air between the fan and each modular brick to cool the electronic components in each of the modular bricks.

Abstract: A modular computing system that includes an enclosure with a rack. A plurality of modular bricks that each include heat-generating electronic components are mounted in the rack. A fan brick that includes at least one fan is also mounted in the rack. The fan brick exchanges air between each modular brick and the fan brick to cool the electronic components in each of the modular bricks.

Abstract: A modular computing system that includes an enclosure, a rack mounted inside the enclosure and a plurality of modular bricks. The modular bricks each include electronic components and are supported by the rack. The computing system further includes a floor tile supporting the enclosure. The floor tile includes a plurality of fans that exchange air with each of the modular bricks to cool the electronic components in each modular brick.

Abstract: System, method and apparatus for compressing and decompressing image data. In an embodiment, a color cell is compressed by: defining at least four luminance levels of the color cell; generating a bitmask for the color cell, the bitmask having a plurality of entries each corresponding to a respective one of the pixels, each of the entries for storing data identifying one of the luminance levels associated with a corresponding one of the pixels; calculating a first average color of pixels associated with a first one of the luminance levels; calculating a second average color of pixels associated with a second one of the luminance levels; and storing the bitmask in association with the first average color and the second average color.

Abstract: A novel packet switched routing architecture for establishing multiple, concurrent communications between a plurality of devices. Any number of devices are coupled to a central packet switched router via links. Due to the nature of these tightly coupled links, high data rates can be achieved between devices and the packet switched router with minimal pins. Any device can communicate to any other device via the packet switched router. The packet switched router has the capability of establishing multiple communication paths at the same time. Hence, multiple communications can occur simultaneously, thereby significantly increasing the overall system bandwidth.

Abstract: A method, system, and program product for designing an electronic circuit. The electronic circuit has a source component, a sink component and a wire connecting the source and sink components. In one aspect, the wire is divided into wire segments and repeater buffers are added to connect the wire segments. The number of repeater buffers is based on the calculated delay of the global net. In another aspect, the metal routes of the wire are widened to reduce delays on a global net. In these ways, the timing goal of the electronic circuit is met, such that an operation in the electronic circuit will complete within one clock cycle.

Abstract: A system and method for rendering with an object proxy. In one embodiment, a method includes forming a set of view textures corresponding to a set of viewing directions; selecting a viewing direction for rendering; selecting at least two view textures from the formed set based on the selected viewing direction; and rendering the object proxy at the selected viewing direction. The rendering step includes applying texture from the selected view textures onto the selected object proxy. The view texture set forming step includes: calculating texture coordinates for the object proxy based on the level of obstruction at different portions of the object proxy and texture packing data; and drawing portions of the object based on the level of obstruction data for the object proxy and based on the texture packing data to obtain a view texture at the selected viewing direction.

Abstract: Methods, systems, and computer program products for blending textures used to render computer generated images are provided. In an embodiment of the invention, a MIP-mapped mask texture is constructed. Each MIP-level of the MIP-mapped mask texture includes texels representative of different mask information. The MIP-mapped mask texture is sampled during rendering to obtain mask information. The obtained mask information is used to blend between textures. The invention is used to blend, for example, between multiple textures wherein, zero, one, or more of the textures are MIP-mapped and/or between different levels of one or more three-dimensional textures. In an embodiment, the most appropriate texture amongst multiple textures, each providing coverage at different resolutions, is selected for a fragment being rendered, thereby avoiding texture scintillation.