Abstract: A compact flat panel color calibration system includes a lens prism optic able to pass a narrow, perpendicular, and uniform cone angle of incoming light to a spectrally non-selective photodetector. The calibration system also includes a microprocessor operable to determine the luminance of the display based upon the information gathered by the photodetector. A software module included in the calibration system is then operable to process the luminance information in order to adjust the flat panel display.

Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem and operating system implementing DMAPI. Threads executing on a metadata client know when a DMAPI event is required, and generate the DMAPI event on their own initiative when necessary. A metadata server maintains DMAPI queues. If the metadata server relocates to another host, the DMAPI events in the DMAPI queues are moved transparently to users.

Abstract: A modular computer system includes at least two processing functional modules each including a processing unit adapted to process data and adapted to input/output data to other functional modules through at least two ports with each port including a plurality of data lines. At least one routing functional module is adapted to route data and adapted to input/output data to other functional modules through at least two ports with each port including a plurality of data lines. At least one input or output functional module is adapted to input or output data and adapted to input/output data to other functional modules through at least one port including a plurality of data lines. Each processing, routing and input or output functional module includes a local controller adapted to control the local operation of the associated functional module, wherein the local controller is adapted to input and output control information over control lines connected to the respective ports of its functional module.

Abstract: A computer graphics display method and system for controlling data visualization in at least one external dimension is provided which allows better querying and navigation of data in external dimension space. A data visualization is displayed in a first display window. A summary window provides summary information on data for the data visualization across one or more external dimensions. First and second controllers are displayed for controlling the variation of the data visualization in respective first and second external dimensions. A user queries the data visualization in the first and second external dimensions by selecting a point in the summary window. A user navigates through the data visualization in the first and second external dimensions by defining a path in the summary window. Grid points are also displayed in the summary window to facilitate data queries and navigation based on actual data points.

Abstract: A method and system for controlling an access to a first memory arrangement and a second memory arrangement. The method and system are adapted for controlling access to the first memory arrangement and to the second memory arrangement. A token is passed from a device associated with the first memory arrangement if the access to at least one portion of the first memory arrangement is completed, and the access to the portion of the memory arrangement is disabled. Then, upon a receipt of the token, the access to at least one portion of the second memory arrangement is enabled.

Abstract: A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers and/or for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. Since the strobe may have a delay that is unknown (due to varying distances from the driver, clock jitter, and/or other causes), it is important to re-synchronize to the internal clock, and to do so with the smallest delay possible. This synchronization is provided in a way that also eliminates potential problems due to bus-master changeover, and in a way that minimizes time-critical signal generation. One aspect provides a method and/or apparatus for reliable data capture.

Abstract: A variable communication systems comprising a plurality of transceivers and a control circuit connected to the transceivers to configure the transceivers to operate in a bi-directional mode and a uni-directional mode at different times using different transfer methods to transfer data.

Abstract: A system, method and computer program product for forming an object proxy. In one embodiment, a method forms an object proxy that approximates the geometry of an object. The method includes forming a volume that encompasses the object, forming an isosurface within the volume, adjusting the isosurface relative to a surface of the object, and pruning the isosurface to obtain the object proxy. An apparatus includes an isosurface former that forms an isosurface within a volume encompassing an object, and an isosurface shaper that adjusts the isosurface relative to the surface of the object and prunes the isosurface to obtain the object proxy.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: The present invention includes one embodiment of a printed circuit board assembly including a printed circuit board, a microprocessor chip, a socket and an actuator for connecting the chip to the printed circuit board, a heat sink for attachment to the top surface of the chip, and a field installable thermal interface phase change pad positioned between the heat sink and the microprocessor chip. The heat sink has an actuator access opening so that the actuator is operable with the heat sink positioned on top of the microprocessor. The connection between the chip and the heat sink is free of alignment features so that they may be separated by twisting the heat sink relative to the chip. The connection between the heat sink and the circuit board is also free of alignment features.

Abstract: A cluster of computer system nodes connected by a storage area network include two classes of nodes. The first class of nodes can act as clients or servers, while the other nodes can only be clients. The client-only nodes require much less functionality and can be more easily supported by different operating systems. To minimize the amount of data transmitted during normal operation, the server responsible for maintaining a cluster configuration database repeatedly multicasts the IP address, its incarnation number and the most recent database generation number. Each node stores this information and when a change is detected, each node can request an update of the data needed by that node. A client-only node uses the IP address of the server to connect to the server, to download the information from the cluster database required by the client-only node and to upload local disk connectivity information.

Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. At least one trusted metadata server assigns a mandatory access control label as an extended attribute of each filesystem object regardless of whether required by a client node accessing the filesystem object. The mandatory access control label indicates the sensitivity and integrity of the filesystem object and is used by the trusted metadata server(s) to control access to the filesystem object by all client nodes.

Abstract: A processor (300) in a distributed shared memory system (10) has ownership of a cache line. The processor modifies the cache line and wishes to update the home memory (17) of the cache line with the modification. The processor (300) generates a return request for routing by a processor interface (24). Meanwhile, a second processor (400) wishes to obtain ownership of the cache line and sends a read request to a memory directory (22) associated with the home memory (17) of the cache line. The memory directory (22) generates an intervention request towards the processor interface (24) corresponding to the last known location of the cache line. The processor interface (24) has now forwarded the return request to the memory directory (22) but subsequent to the read request from the second processor (400).

Abstract: A system (10) for display distortion correction includes a database (18) that stores one or more pixel correction vectors (40) and one or more sub-pixel correction vectors (42). The system (10) also includes a buffer (14) that receives and stores an input image data unit (32) including a plurality of pixels. Furthermore, the system includes a system controller (12) that is coupled to the database and to the buffer. The system controller (12) generates a coarsely-corrected image data unit by mapping one or more pixels of the coarsely-corrected image data unit to corresponding pixels of the input image data unit (32) according to corresponding pixel correction vectors (40). Each pixel correction vector (40) is associated with a particular pixel of the coarsely-corrected image data unit. The system also includes an interpolation filter (16) that is coupled to the system controller (12) and the database (18).

Abstract: Compositors are identified in a manner that defines the position of the compositor in the compositor tree. Each compositor has its own “unique compositor identifier”. Starting at the most downstream compositor, it transmits its unique compositor identifier to all upstream compositors directly coupled to it. The upstream compositors receive the unique compositor identifier from the most downstream compositor. Each of the upstream compositors appends its unique compositor identifier to the unique compositor identifier received from the most downstream compositor to produce a “compositor tree compositor identifier”. The compositor tree compositor identifier identifies both the compositor and its position in the compositor tree. This enables an application to detect the structure of the compositor tree so that the application can determine a desired tiling configuration that exploits the structure of the compositor tree.

Abstract: A large area wide aspect ratio flat panel display having high resolution for high information content display. The present invention includes a liquid crystal flat panel display monitor having a wide aspect ratio. In one embodiment, the wide aspect ratio is substantially 1.6:1, having 1,600 pixels across the horizontal and 1,024 across the vertical. In this embodiment, the present invention is an SXGA-wide flat panel display monitor having high resolution for high information content display. The monitor of the present invention is particularly well suited for the display of text, graphics and other types of still and/or motion audio/visual works. The wide aspect ratio allows the display of multiple pages, side-by-side, thereby facilitating certain tasks such as desktop publishing, presentation of interactive windows, presentation of menus, chart viewing, digital photography, tactical military displays and weather and aircraft monitoring.

Abstract: A memory access arbitration scheme is provided where transactions to a Shared memory are stored in an arbitration queue. Prior to arbitration, the transactions are compared against the contents of cache memory, to determine which transactions will hit in cache, which will miss and which will be victims. Also prior to arbitration, the entries in the arbitration queue are grouped according to a transaction parameter, such as DRAM bank, Write to Bank, Read to Bank, etc. Arbitration is the performed among those groups which are ready for service. From the group winning arbitration, the oldest transaction is selected for servicing. Preferably, a collapsible queuing structure and method is used, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries.

Abstract: A can test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.

Abstract: A computer enclosure and method for manufacture include a computer housing and an outer layer, the housing having an inner surface and an outer surface, the outer layer having a first surface and a second surface, wherein the first surface of the outer layer is coupled to the outer surface of the housing and covers a substantial portion of the outer surface, and the second surface of the outer layer has a graphic design applied thereto.

Abstract: A method for efficiently simulating memory structures of a sequential circuit for design verification of the sequential circuit. The method is implemented by an computer system having a processor coupled to a memory via a bus, the memory storing computer readable code which when executed by the processor cause the computer system to perform the steps of the memory structure simulation method. The method includes accessing a netlist description of a sequential circuit, wherein the description is for realizing the sequential circuit in a physical form. Memory elements included within the description are identified. For these memory elements, inputs to the memory elements and outputs from the memory elements are identified. Using this information, the memory elements are grouped into at least one group of functionally related memory elements. Subsequently, the memory elements of the one or more groups are collectively addressed as a group.