Abstract: A ground bracket and method for grounding an electronic device to a structure such as a rail, rack or cabinet. According to one aspect of the invention the ground bracket has a first conductive surface for use in coupling the bracket to the structure and an arcuate portion conductively coupled to the first conductive surface for contacting an electronic device. In another embodiment, a bracket includes a first surface for coupling to a rack, and a portion positioned proximal a computer component that includes a rotatable fastening mechanism for coupling to the computer component.

Abstract: A method and computer program product, within an optimizing compiler, for the global minimization of sign-extension and zero-extension operations in generated code during compilation. The method and computer program product allows, for example, 64-bit compilers targeting the Intel IA64 architecture to improve their SPECint benchmarks by reducing the number of sign-extension and zero-extension operations in the global and intra-procedural scope, thus, speeding up the execution of the compiled program.

Abstract: The present invention is directed to a method and system for sharing a data memory among a plurality of processors in a computer system. In the system and method of the present invention, a plurality of processors are coupled to a data memory for accessing the data memory in N-bit bandwidth. The present invention receives an active signal for accessing the data memory from the plurality of processors. A processor requesting accessing to the data memory asserts an active signal. Among the processors asserting active signals, a processor is selected as a memory master to the data memory. The present invention then transfers the N-bit wide data between the selected processor and the data memory in a time slot defined by a clock cycle. Only one processor is allowed access to the data memory during a given time slot. In the preferred embodiment of the present invention, the N-bit bandwidth is large enough to accommodate the data requirements of all the processors.

Abstract: A compiler for compiling source code whereby the compiled source code is optimized by performing outer loop unrolling (a generalization of “unroll and jam” on selected loop nests. The present invention allows any arbitrarily deep loop nests with non-varying loop bounds to be properly unrolled even in the presence of imperfectly nested code. This is accomplished for two-deep loop nests by transforming the code into multiple adjacent loop nests. In the transformed code, the imperfect code is isolated so that one of the adjacent loops nests has none, and thus can be unrolled and jammed. For three-deep or greater loop nests, the process is repeated recursively from the outer-most loop. The present invention also allows outer loop unrolling for two-deep loop nests with convex bounds, even with the presence of imperfectly nested code. This is accomplished by identifying strips of code which do not contain imperfectly nested code. An unroll and jam operation is executed for the identified strips.

Abstract: A node controller (12) includes a processor interface unit (24) that receives an interrupt signal (50). The processor interface unit (24) includes a register (52) with a forward enable bit (54). In response to the forward enable bit (54) being set, the processor interface unit (24) generates a forward interrupt signal (56) for transfer to an input/output interface unit (26) of the node controller (12). The input/output interface unit (26) generates an interrupt request for transfer to a remote node controller. The input/output interface unit (26) includes an interrupt destination register (58) that includes an identity of a particular remote node controller and associated processor interface unit to which the interrupt request is to be transferred. The remote node controller having a processor attached thereto to handle the interrupt request.

Abstract: A method and system for updating the colorimetric characteristics of a flat panel display over the display's entire lifetime. An advantage of the present invention is that the useful life and the color accuracy of a flat panel display can be extended. In one embodiment of the invention, an initial set of luminance data of a flat panel monitor is programmed into addressable memory locations within that monitor. Thereafter, the luminance output of the lamps of the flat panel monitor is tracked with luminance or colorimetric measuring devices. According to the present invention, the luminance data are used in determining the correlation between voltage settings of the lamps and the color characteristics of the display such as color temperature. By measuring the luminance of the display periodically, a precise and accurate color profile of the flat panel display can be maintained.

Abstract: A low cost high performance three dimensional (3D) graphics system is disclosed that can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a color television set. The richly featured high performance low cost system is intended to give consumers the chance to interact in real time right inside magnificent virtual 3D worlds to provide a high degree of image realism, excitement and flexibility. An optimum feature set/architecture (including a custom designed graphics/audio coprocessor) provides high quality fast moving 3D images and digital stereo sound for video game play and other graphics applications.

Abstract: New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion.

Abstract: A method for parameterizing a subdivision mesh in a computer system, the subdivision mesh comprising at least two faces, at least two faces sharing an edge, includes assigning a unique index for each of the at least two faces, assigning, for each of the at least two faces, a first (u) and a second (v) parameter to uniquely parameterize each point on a respective face, each respective u and v parameters for a respective face also being assigned the unique index for that respective face; and at a vertex shared by two faces sharing an edge, setting a first bound for each of the u and v parameters for each of the two faces, and for each of the same two faces, at a vertex not shared by the two faces, setting a second bound for each of the u and v parameters.

Abstract: A modular, scalable high-bandwidth computer architecture. A single integrated router/bridge ASIC defines a family of peripheral controllers that accept high-speed packet switched data, either for routing to other, identical controllers, or for routing to on-board PCI buses, or a combination of the two destinations, depending on the number of ASICs employed and their selectable configuration.

Abstract: A method and apparatus for providing efficient and accurate electronic data transmission of information on a data bus in the presence of noise. Data signals are received on a plurality of input lines by a spacial derivative encoder. The spacial derivative encoder encodes the signals and transmits them to a receiver having a spacial derivative decoder. The spacial derivative decoder then decodes the signals. Minimal overhead is required as for n input lines only n+1 lines are needed to transmit each of the encoded signals.

Abstract: A system and method for determining a repeater allocation region is disclosed. A path delay equation describing a path delay from a driver to a gate is formulated. A delay constraint is applied to the path delay equation. A repeater allocation region indicating a position of a repeater is determined from the path delay equation.

Abstract: The present invention is a system that allows a user to paint surface related attributes just like texture is painted. The painting actions are in the form of scripts that the user can provide and which are interpreted during painting.

Abstract: A method for implementing edge blending between a first and second video frame to create a seamless multichannel display system. The method is implemented in a graphics computer system including a processor coupled to a memory via a bus. Within the computer system, a first video frame is rendered for display on a first video channel. A second video frame is rendered for display on a second channel. A first overlap region is rendered onto the first frame to obtain a first blended video frame. A second overlap region is blended onto the second frame to obtain a second blended video frame. The first blended video frame from the first channel and the second blended video frame from the second channel are then combined such that the first overlap region and the second overlap region correspond, thereby forming a seamless junction between the first blended frame and the second blended frame and implementing a high fidelity multichannel display.

Abstract: A node controller (12) includes a processor interface unit (24), a crossbar unit (26), and a memory directory interface unit (22). Request and reply messages pass from the processor interface unit (24) to the crossbar unit (26) through a processor interface output queue (52). The processor interface unit (24) writes a request message into the processor interface output queue (52) using a processor interface clock to latch a write address from a write address latch (62) in a synchronizer (60). The write address is encoded by a Gray code counter (64) and latched by a first sync latch (66) and a second sync latch (18) using a core clock of the crossbar unit (30). The output of the second sync latch (68) provides one of the inputs to a read address latch (70) using the core clock of the crossbar unit (30).

Abstract: A structure and method thereof for providing an electrically conductive path between a first conductive point and a second conductive point. The structure includes an insulating material disposed between the first conductive point and the second conductive point. A dipole material is distributed within the insulating material. The dipole material is comprised of randomly oriented magnetic particles. The magnetic particles in a selected localized region of the insulating material are aligned to form an electrically conductive path between the first conductive point and the second conductive point through the insulating material.

Abstract: A system for color balancing within a liquid crystal flat panel display unit. The present invention includes a method and system for altering the brightness of two or more light sources, having differing color temperatures, thereby providing color balancing of a liquid crystal display (LCD) unit within a given color temperature range. The embodiments operate for both edge and backlighting systems. In an embodiment, two planar light pipes are positioned, a first over a second, with an air gap between. The first light pipe is optically coupled to receive light from a first light source having a color temperature above the predetermined range and the second light pipe is optically coupled to receive light from a second light source having a color temperature below the predetermined range.

Abstract: A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the input queue (12). The input queue (12) queues commands and requests a number of output queue credits in response to receiving a command. The input queue (12) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue (14) queues commands and requests a number of output queue credits in response to receiving a command.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.