Abstract: A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the input queue (12). The input queue (12) queues commands and requests a number of output queue credits in response to receiving a command. The input queue (12) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue (14) queues commands and requests a number of output queue credits in response to receiving a command.

Abstract: An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of the logic for comparing exponents represents the most significant bits of the result of the integer operation. The output of the logic for adding co-efficients represents the least significant bits of the result of the integer operation. If there is a carry from the logic for adding co-efficients, the value of the carry is added to the partial result representing the most significant bits of the integer operation.

Abstract: A data synchronizer (60) receives a data ready signal (40) at a selector (82). The selector (82) selects either the data ready signal (40) or a delayed version of the data ready signal (40) in response to a speed select signal (88) determined according to a clock speed of a receive core clock (52). The selector (82) provides a select signal (92) to a first latch unit (94) and a second latch unit (96). The first latch unit (94) generates a latched select signal (A) that is provided as a receive data valid signal (48) by a signal generator (108) in response to a slow clock rate for the receive core clock (52). The second latch unit (96) generates a delayed select signal (B) that is used by the signal generator (108) to remove an extra width inserted into the latched select signal (A) prior to providing the receive data valid signal (48) in response to a fast clock rate for the receive core clock (52).

Abstract: Apparatus and methods for reducing circuit board flexing is presented. The apparatus is fastened to a printed circuit board to provide rigid support for reducing bending and flexing. In one embodiment, a rigid frame is provided that is adapted to be fastened to one or more components and to be fastened to a printed circuit board. The frame is adapted to elevate the attached component from the PCB surface allowing components to be mounted on the PCB therewith. The frame is adapted to occupy minimal printed circuit board surface area so as not to displace electronic components. In another embodiment, an elongated truss-like stiffener is provided that is adapted to be fastened to one side of the printed circuit board and adapted to span the printed circuit board. The elongated stiffener is adapted to have an open structure to minimize cooling flow disturbance and weight. The elongated stiffener includes a plurality of legs forming a truss-like structure.

Abstract: The present invention is a system that produces a position of a rigid object, such as a button, on a deformed model, such as an animated piece of cloth, at each cycle in an animation of the model by isotropically finding a linear approximation of the deformation at the model and finding a rotation of the object allowing attachment of the object to the model. The system removes shear and scaling from a linear transformation of an average deformation of the model. A volumetric area of the deformed model in which the object will reside and which is used for the position determination is specified essentially as a mapping of the object onto the model. The average deformation of the area is calculated and the linear transformation of the object is performed with the average deformation. In finding the rotation a rotation characteristic matrix is created and Eigen vectors or directions are extracted and correspond to the rotation.

Abstract: Apparatus, methods, data structures, and systems are provided for subdividing input data associated with a first software program into job quanta, wherein each job quantum is operable to be executed by a separate software program residing on a different processing element from the first software program. The first software program and the separate software program execute substantially in parallel and output data associated with the executions of the programs are assembled into a single coherent presentation or results data. Moreover, the software programs may be threaded or non-threaded.

Abstract: A system that includes a pop-up graphical user interface that includes menu bars overlapping marking menu zones. The interface pops up at the current position of the cursor when the space bar is held down. The menu bars are positioned around a central marking zone with the common menu bars located above the central zone and task specific menu bars located below the central zone. The common application menu bar is positioned outer most and the common window menu bar is located inner most. The menu bars are sized in a “stair-step” pattern and the commands therein are left and right justified to fill the menu bar evenly. The menu bar menu items are accessed just like menu bar items typically found at the top of windows. The menu bars mimic the menu bars that a user may need to use during tasks that users typically perform using the menu bars found in application windows.

Abstract: A composite delay line includes a first and a second delay line connected to a multiplexer. The multiplexer has a first and a second input. The first delay line includes an input, an output and first control means for controlling delay. The second delay line includes an input, an output and second control means for controlling delay. The output of each delay line is connected to the input of the multiplexer. Control logic connected to the first control means selects a delay through the first delay line. Control logic connected to the second control means selects a delay through the second delay line. Control logic connected to the multiplexer selects between the output of the first delay line and the second delay line.

Abstract: An improved support bracket for supporting electronic devices provides improved adjustability and alignment. The support bracket includes a front surface and a rear surface each including a portion having at least one threaded hole and a support portion between the front surface and rear surface for supporting an electronic device. The support bracket includes a side portion having a mechanism for coupling the side portion to a structure, a guide portion and a support portion for supporting an electronic device.

Abstract: A distributed shared memory multiprocessor computer system is provided, which has a number of processors and is divided into partitions. Each partition has within it one or more of the processors, and may also have memory or cache and other related hardware. Although each partition works together and communicates with other partitions to share computational load, the partitions each are independently operable and execute an independent copy of the operating system. The partitions comprise additional features to enable removal of a partition from the operating computer system, and to enable insertion of hardware into the operating computer system.

Abstract: Apparatus and methods for reducing circuit board flexing is presented. The apparatus is fastened to a printed circuit board to provide rigid support for reducing bending and flexing. In one embodiment, a rigid frame is provided that is adapted to be fastened to one or more components and to be fastened to a printed circuit board. The frame is adapted to elevate the attached component from the PCB surface allowing components to be mounted on the PCB therewith. The frame is adapted to occupy minimal printed circuit board surface area so as not to displace electronic components. In another embodiment, an elongated truss-like stiffener is provided that is adapted to be fastened to one side of the printed circuit board and adapted to span the printed circuit board. The elongated stiffener is adapted to have an open structure to minimize cooling flow disturbance and weight. The elongated stiffener includes a plurality of legs forming a truss-like structure.

Abstract: A driver operable with two power supplies, and provides, among other things, a high data communication rate, stabilized operating parameters including voltage output high, voltage output low, and on resistance, and edge rate over a wide range of variations in manufacturing process, operating voltages and temperature.

Abstract: A printed circuit card carrier permits exchange of a card during continuous operation of electronic equipment, and thus without the need to remove an upper part of the enclosure to gain access to the card for upward removal from a motherboard connector. The carrier includes a movable printed circuit card holder that slides along the carrier, perpendicularly towards and away from the motherboard. An actuator accessible from outside the equipment and the holder are coupled together such that motion of the actuator is directed into perpendicular sliding motion of the holder. This either removes the printed circuit card from the motherboard connector or installs it into connector, depending on the direction of motion of the actuator. The carrier is particularly adapted for cards meeting the PCI standard.

Abstract: In a method for providing concurrent access to virtual memory data structures, a lock bit for locking a virtual page data structure is provided in a page table entry of a page table. The page table is configured to map virtual pages to physical pages. Then, a first thread specifying an operation on the virtual page data structure is received. The first thread is provided exclusive access to the virtual page data structure by setting the lock bit in the page table entry such that other threads are prevented from accessing the virtual page data structure. A wait bit also may be provided in the page table entry to indicate that one or more of the other threads are in a wait queue when the first thread has exclusive access to the data structure. When the first thread no longer needs exclusive access to the data structure, a second thread is selected from among the other threads and is provided with exclusive access to the data structure.

Abstract: A system and method of controlling delay in a delay line. In a delay line having a system mode and an oscillator mode, wherein the delay line delays a signal as a function of a delay code, the method comprises setting the delay code, placing the delay line in oscillator mode, determining frequency of oscillation of the delay line, comparing the frequency of oscillation to a target frequency and adjusting the delay code until the frequency of oscillation of the delay line is substantially equal to the target frequency.

Abstract: The invention described herein is a method, system, and computer program product for the design and fabrication of the surfaces of an object. The process begins by using a CAD process to design surfaces of the object. In particular, the surfaces are modeled using developable surfaces only. The intersections of the developable surfaces are then calculated. Any excess surface area of the developable surfaces is then trimmed. The boundaries of each developable surface are abstracted to produce a two-dimensional planar model of each developable surface. From each planar model, a full-sized two-dimensional shape can then be fabricated in proportion to the planar model. Each fabricated shape can then be bent in accordance with the corresponding developable surface of the CAD model. Finally, the edges of the fabricated shapes are attached as determined by the calculated intersections of the developable surfaces of the CAD model.

Abstract: A cable connector backshell assembly for high frequency applications requiring reduced electromagnetic emissions. Aspects include providing sufficient physical spacing and electrical isolation between the signal conductors and the housing to meet EMI standards for HIPPI-6400 connector assemblies. One embodiment includes spring preloading of the electrical connecter. One embodiment includes a longitudinally floating connector.

Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Abstract: A method for minimizing ECC bits in variable sized data formats is provided that comprises determining the number of ECC bits needed for each of a plurality of data formats and creating a common data representation for using a single implementation of error detection and correction logic for all of the plurality of data formats. The method then chooses an ECC matrix and default values for unused data bits in the common data representation such that any ECC bits beyond the minimum required for that sized data format will have known values thereby allowing smaller data formats to go through the error detection and correction logic using the common data representation. The method then retrieves a data entry having one of the plurality of data formats and formats the data entry into the common data representation.