Abstract: Methods and apparatus for maintaining and utilizing system memory defect tables that store information identifying defective memory locations in memory modules. For some embodiments, the defect tables may be utilized to identify and re-map defective memory locations to non-defective replacement (spare) memory locations as an alternative to replacing an entire memory module. For some embodiments, some portion of the overall capacity of the memory module may be allocated for such replacement.

Abstract: The system includes a chassis and a printed circuit board (e.g., a motherboard) that is attached to the chassis. The system further includes an actuator that is slidably engaged with the chassis and a cam plate that is rotatably engaged with the chassis. The actuator engages the cam plate such that maneuvering the actuator rotates the cam plate. The system further includes a blade (e.g., an electronic module) which is slidably engaged with the chassis such that the blade slides in a first direction within the chassis as the blade is inserted into the chassis. The blade is inserted into the chassis until the blade engages the cam plate. The cam plate engages the blade such that rotation of the cam plate causes the blade to continue to move in the first direction and engage the printed circuit board.

Abstract: A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.

Abstract: A system and method for distributing data (e.g., imaging data such as pixels, or 3D graphics data such as points, lines, or polygons) from a single or a small number of data sources to a plurality of graphical processing units (graphics processors) for processing and display is presented. The system and method provide a pipelined and multithreaded approach that prioritizes movement of the data through a high-speed multiprocessor system (or a high-speed system of networked computers), according to the system topology. Multiple threads running on multiple processors in shared memory move the data from a storage device (e.g., a disk array), through the high-speed multiprocessor system, to graphics processor memory for display and optional processing through fragment programming. The data can also be moved in the reverse direction, back through the high-speed multiprocessor system, for storage on the disk array.

Abstract: The present invention is a system that allows a number of 3D volumetric display or output configurations, such as dome, cubical and cylindrical volumetric displays, to interact with a number of different input configurations, such as a three-dimensional position sensing system having a volume sensing field, a planar position sensing system having a digitizing tablet, and a non-planar position sensing system having a sensing grid formed on a dome. The user interacts via the input configurations, such as by moving a digitizing stylus on the sensing grid formed on the dome enclosure surface. This interaction affects the content of the volumetric display by mapping positions and corresponding vectors of the stylus to a moving cursor within the 3D display space of the volumetric display that is offset from a tip of the stylus along the vector.

Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).

Abstract: Mapping of cacheable memory pages from other processes in a parallel job provides a very efficient mechanism for inter-process communication. A trivial address computation can then be used to look up a virtual address that allows the use of cacheable loads and stores to directly access or update the memory of other processes in the job for communication purposes. When an interconnection network permits the cacheable access of one host's memory from another host in the cluster, kernel and library software can map memory from processes on other hosts, in addition to the memory on the same host. This mapping can be done at the start of a parallel job using a system library interface. A function in an application programming interface provides a user-level, fast lookup of a virtual address that references data regions residing on all of the processes in a parallel job running across multiple hosts.

Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.

Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.

Abstract: A system and method of reducing back flow in an air mover having one or more blades is described. A flap is attached to a blade of the air mover such that, when back flow occurs, the flap obscures all or a portion of the space between blades during back flow.

Abstract: A memory access arbitration scheme is provided where transactions to a shared memory are stored in an arbitration queue. A collapsible queuing structure and method are provided, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries. A queuing circuit having a plurality of registers interconnected by 2:1 multiplexers is also provided. The circuit is arranged such that each register receives either its own current contents or the contents of a higher order register during each register write cycle.

Abstract: A compact flat panel color calibration system includes a lens prism optic able to pass a narrow, perpendicular, and uniform cone angle of incoming light to a spectrally non-selective photodetector. The calibration system also includes a microprocessor operable to determine the luminance of the display based upon the information gathered by the photodetector. A software module included in the calibration system is then operable to process the luminance information in order to adjust the flat panel display.

Abstract: The present invention provides a method and system for presenting three-dimensional computer graphics images using multiple graphics processing units. The dimensions of the scene to be rendered are bounded by a rectangular volume decomposed into rectangular subvolumes. Vertices of graphics primitives are compared with subvolume boundaries to determine to which subvolume a graphics primitive should be assigned. A GPU is assigned to each subvolume to render the graphics data that lies within it. A viewing position point is determined and communicated to each GPU. Rendered graphics data from each GPU are ordered based upon the viewing position Outputs of the individual GPUs are combined by blending within an image combiners. Outputs of image combiners can be presented for viewing or further combined in a subsequent stage image combiner.

Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.

Abstract: A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the instruction to a selected one of a plurality of unique physical registers. The selected unique physical register is used to hold a result according to execution of the instruction. An indication is provided to the mapping table when the selected unique physical register contains the result. The result is then moved to a fixed status register. The selected unique physical register is then returned for later reuse and the next consecutive physical register is selected for the next instruction such that physical registers are used in order. An indication is provided for output to inform whether the result is in the selected unique physical register or has been moved to the fixed status register.

Abstract: A visual server system (10) includes a server (12) having a graphics application (20). The graphics application (20) generates image content and position information. The server (12) streams the image content and the position information for transport over a network link. A plurality of remote clients (14) can receive the image content and position information from the server (12) over the network link. Each of the plurality of remote clients (14) may provide input parameters to the graphics application (20). The input parameters can provide adjustments to the image content and position information provided to each of the plurality of remote clients (14). The graphics application (20) selects from among the input parameters provided by the plurality of remote clients (14) for adjusting the image content and the position information provided to the remote clients (14).

Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

Abstract: A method is disclosed for culling an object database in a graphics processing system. In one embodiment, the method comprises encoding per-object parameters and culling parameters. The per-object parameters are encoded in texture format thereby creating at least one per-object texture containing the encoded per-object parameters. Next, a fragment program used in a fragment processor of the GPU is optionally updated. The updated fragment program embodies a culling operation. A polygon is then rendered, wherein the rendering step includes per-fragment operations. During the per-fragment operations, the updated fragment program is executed. The culling operation embodied therein (i) accesses the culling parameter, (ii) samples the per-object textures, and (iii) produces cull results for a set of database objects. In this fashion, the fragment processor in the GPU is leveraged to perform computationally intensive culling operations.

Abstract: An apparatus and method of controlling data sharing in a shared memory computer system transfers control of a cache coherency directory (entry) to a node having control of the data. Specifically, the plurality of nodes includes a home node and a second node. The home node has given data in a cache line in its memory, and also has a directory identifying the state of the cache line. The method and apparatus thus detect a request for ownership of the cache line from the second node, and enable the second node to control the directory after receipt of the request.

Abstract: An apparatus and method of processing object data (e.g., a scene having one or more objects) logically divide the object space into a plurality of contiguous (or noncontiguous) portions. At least two portions each have object data for such object(s). The apparatus and method also determine a positional priority of the at least two portions of the object space for a given viewpoint. Next, the apparatus and method merge rendered object data after at least some of the object data is rendered. This merging is based upon the positional priority of the at least two portions.