Abstract: A cpu-set type multiprocessor system allows a cpu of a cpu-set that has a hardware exception to disable itself and notify the system. The system assigns processes of the cpu-set that include the problem cpu to another cpu-set. The disabling of the problem cpu and transfer of the related processes to another cpu-set allows the system to failsoft so that other cpu-sets the multiprocessor system can continue to run and a recovery of the processes being run on the problem cpu-set occurs.

Abstract: A method for communicating video data is provided that includes generating a plurality of error correction code bits and positioning the error correction code bits in a stream of image data such that the stream of image data is encoded. The stream of image data may then be received and encoded in order to convert the stream of image data into a digital visual interface (DVI) format. The stream of image data may then be decoded such that the stream of image data may be displayed in the DVI format. The stream of image data may then be received and checked for one or more errors using the error correction code bits.

Abstract: The present invention is a system that receives data in different formats from different devices/applications in the format native to the devices/applications and fuses the data into a common shared audio/video collaborative environment including a composite display showing the data from the different sources in different areas of the display and composite audio. The common environment is presented to users who can be at remote locations. The users are allowed to supply a control input for the different device data sources and the control input is mapped back to the source, thereby controlling the source. The location of the control input on the remote display is mapped to the storage area for that portion of the display and the control data is transmitted to the corresponding device/application.

Abstract: A modular computer system includes at least two processing functional modules each including a processing unit adapted to process data and adapted to input/output data to other functional modules through at least two ports with each port including a plurality of data lines. At least one routing functional module is adapted to route data and adapted to input/output data to other functional modules through at least two ports with each port including a plurality of data lines. At least one input or output functional module is adapted to input or output data and adapted to input/output data to other functional modules through at least one port including a plurality of data lines. Each processing, routing and input or output functional module includes a local controller adapted to control the local operation of the associated functional module, wherein the local controller is adapted to input and output control information over control lines connected to the respective ports of its functional module.

Abstract: A method and apparatus for maintaining data coherency in a computer system having a plurality of nodes forms a directory by grouping the nodes into a plurality of hierarchical groups of two or more levels. The method and apparatus also 1) set the directory to have data relating to a first set of groups within a first level, and 2) determine if a requesting node requesting data is a member of one of the first set of groups. The directory then is set to have data relating to a second group of nodes if the requesting node is determined not to be a member of the first set of groups within the first level. The second group of nodes is in a higher level than the first level.

Abstract: A method is disclosed for culling an object database in a graphics processing system. In one embodiment, the method comprises encoding per-object parameters and culling parameters. The per-object parameters are encoded in texture format thereby creating at least one per-object texture containing the encoded per-object parameters. Next, a fragment program used in a fragment processor of the GPU is optionally updated. The updated fragment program embodies a culling operation. A polygon is then rendered, wherein the rendering step includes per-fragment operations. During the per-fragment operations, the updated fragment program is executed. The culling operation embodied therein (i) accesses the culling parameter, (ii) samples the per-object textures, and (iii) produces cull results for a set of database objects. In this fashion, the fragment processor in the GPU is leveraged to perform computationally intensive culling operations.

Abstract: A system and method are described herein for controlling the white balance and providing gamma correction without compromising gray-scale dynamic range in a flat panel liquid crystal display (LCD). According to one embodiment of the present invention, the flat panel LCD includes electronic circuitry for coupling to a host computer to receive a white-balance adjustment control signal, and electronic circuitry for receiving image data to be rendered on the flat panel LCD. Further, the flat panel LCD of one embodiment is configured for coupling to a color-sensing device to receive optical characteristics data of the flat panel LCD detected by the color-sensing device. The white balance adjustment mechanisms include the provision of two or more light sources of differing color temperature, whose brightness can be independently varied (and distributed through a light distribution mechanism) to adjust color temperature without altering the grayscale resolution of the RGB colors.

Abstract: An apparatus for controlling a hot plug bus slot on a bus has an input for receiving a set of float signals (i.e., the set may have one or more float signals), and a driver having an output electrically couplable with the bus. The apparatus also has float logic operatively coupled with the input. The float logic is responsive to the set of float signals to cause the output to float at a high impedance in response to receipt of the set of float signals.

Abstract: A computer system (10) includes a bus controller (12), a bus (14), a plurality of processing devices (16) and a plurality of enabling switches (18). Each enabling switch (18) corresponds to a separate one of the processing devices (16). Each processing device (16) sends an access request (24) to arbitration logic (22) in the bus controller (12), requesting access to the bus (14). The arbitration logic (22) selects one of the access requests (24) according to a priority protocol. The arbitration logic (22) generates a control signal (20) associated with the selected access request (24). The control signal (20) is provided to the enabling switch (18) corresponding to the processing device (16) that sent the selected access request (24). The enabling switch (18) enables access to the bus (14) for the processing device (16) in response to the control signal (20).

Abstract: An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.

Abstract: In one embodiment, an apparatus includes a requester node to transmit a request for data in a memory. The apparatus also includes a service node that includes the memory. The service node receives the request for the data, wherein the service node is to set a congestion flag in response to the request sent back to the requester node upon determining that access to the data is congested. The requester node is to freeze priority updates for the data upon receipt of the congestion flag.

Abstract: A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments.

Abstract: A system and method for allocating computing resources. The system obtains a current set of connections from the matrix switch and then renders a display which reflects the current state of the connections. Source and destination ports are displayed as icons with each icon bearing a label that describes the corresponding source or destination. In some embodiments, a user clicks on a source icon and drags it onto a destination icon to route a particular source to a destination. Dragging a source icon off of a destination icon breaks the connection between the source and destination. The display uses a variety of icons, colors, and grouping schemes to indicate other attributes of the ports, such information regarding X Server configuration, physical location of destination devices, and user login sessions.

Abstract: A method and apparatus for providing efficient and accurate electronic data transmission of information on a data bus in the presence of noise. Data signals are received on a plurality of input lines by a spacial derivative encoder. The spacial derivative encoder encodes the signals and transmits them to a receiver having a spacial derivative decoder. The spacial derivative decoder then decodes the signals. Minimal overhead is required as for n input lines only n+1 lines are needed to transmit each of the encoded signals.

Abstract: A method and apparatus for processing a primitive (for potential display as a part of a graphical image on a display device) cause attribute data to be received by a graphics processor as a function of whether the primitive is capable of being viewable in the graphical image on the display device. Before taking that action, however, the method and apparatus assemble the primitive as a function of its positional data, and then determine if the primitive is capable of being viewable in the graphical image on the display device.

Abstract: A system and method for managing graphics applications include the capability to manage the conveyance of graphics data from an aware graphics application to a plurality of graphics pipes and to manage the conveyance of graphics data from an unaware graphics application to a plurality of graphics pipes. The system and method also include the capability to coherently manage the windows for aware and unaware applications.

Abstract: A display is capable of displaying images in response to signals of a plurality of signal formats. The display includes a controller that is coupled to a plurality of image data interfaces. When the plurality of image data interfaces are simultaneously operating, the controller selects one of the plurality of image data interfaces according to preference variables associated with each of the plurality of image data interfaces. Each of the preference variables may indicate a relative priority of an image data signal format associated with the corresponding image data interface. In addition, each of the preference variables may indicate one or more performance metrics associated with the quality of image data signals received from the corresponding image data interface.

Abstract: A system and method are described herein for controlling the white balance and providing gamma correction without compromising gray-scale dynamic range in a flat panel liquid crystal display (LCD). According to one embodiment of the present invention, the flat panel LCD includes electronic circuitry for coupling to a host computer to receive a white-balance adjustment control signal, and electronic circuitry for receiving image data to be rendered on the flat panel LCD. Further, the flat panel LCD of one embodiment is configured for coupling to a color-sensing device to receive optical characteristics data of the flat panel LCD detected by the color-sensing device. The white balance adjustment mechanisms include the provision of two or more light sources of differing color temperature, whose brightness can be independently varied (and distributed through a light distribution mechanism) to adjust color temperature without altering the grayscale resolution of the RGB colors.

Abstract: A liquid cooled heat sink for electronic circuit boards is described. A heat sink base includes a liquid cooling arrangement to remove heat from the base. An arrangement of cooling fins extends from the base, and at least one surface of each fin includes a thermal interface layer. The arrangement is adapted so that the fins fit between parallel electronic circuit boards such that for each circuit board, a thermal contact layer of a fin contacts multiple components on the circuit board so as to conduct heat from the components into the fin, which in turn transfers heat to the heat sink base.

Abstract: A cable connector backshell assembly for high frequency applications requiring reduced electromagnetic emissions. Aspects include providing sufficient physical spacing and electrical isolation between the signal conductors and the housing to meet EMI standards for HIPPI-6400 connector assemblies. One embodiment includes spring preloading of the electrical connector. One embodiment includes a longitudinally floating connector.