Patents Assigned to Silicon Graphics
  • Publication number: 20060227245
    Abstract: Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end counter. The front-end counter represents an unadjusted system time (UST). The media device obtains a frame of data to be displayed from a computer system. The media device also receives a back-end synchronization signal that periodically increments a back-end counter each time a frame of data is to be displayed. The back-end counter represents a media stream count (MSC). UST and MSC data are periodically transmitted to the computer system for analysis and use by a synchronization algorithm. Specifically, UST is transmitted to the computer system each time a frame of data is obtained, and a UST/MSC pair is transmitted to the computer system each time a frame of data is displayed.
    Type: Application
    Filed: April 11, 2005
    Publication date: October 12, 2006
    Applicant: Silicon Graphics, Inc.
    Inventors: Michael Poimboeuf, Francis Bernard, Kevin Smith, Parkson Wong, Todd Stock, William Lawson
  • Patent number: 7120906
    Abstract: A method and computer program product, within an optimizing compiler, for precise feedback data generation and updating. The method and computer program uses instrumentation and annotation of frequency values to allow feedback data to stay current during the multiple optimizations that the program code undergoes during compilation. Global propagation of known precise feedback values are used to replace approximate and unavailable values, and global verification of feedback data after optimization to detect discrepancies is employed. The method and computer program also provides improved instrumentation to anticipate cloning when code is cloned during ceratin compiler optimizations and handles inlined procedures. The result is compiled executables with improved SPECint benchmarks.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: October 10, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: David L. Stephenson, Raymond Lo, Sun Chan, Wilson Ho, Chandrasekhar Murthy
  • Patent number: 7100018
    Abstract: A system and method for encoding page size information has been described herein. In one embodiment, the method includes determining whether a virtual address is stored in a translation lookaside buffer (TLB), the TLB including a plurality of entries, wherein the entries include a minimum virtual page number bit string and a variable bit string. In one embodiment the method also includes determining whether the first bit string matches the minimum virtual page number bit string of one of the entries. In one embodiment, if the first bit string matches the minimum virtual page number bit string of one of the entries, the method includes decoding a page size stored in the variable portion of the matching entry and a 1-bit field associated with the matching entry, wherein the decoding determines a set of bits of the variable bit string.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: August 29, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: David Zhang, Mahdi Seddighnezhad
  • Patent number: 7092983
    Abstract: A computerized method for remotely rendering a render job includes receiving a render job submitted by a client at a first rendering site, the render job associated with at least one file stored at the first rendering site. The file stores information necessary to render the render job. The method also includes transferring the render job from the first rendering site to a second rendering site, the second site remote from the first site. The method further includes transmitting a copy of the associated file from the first rendering site to the second rendering site, storing the copy of the associated file at the second rendering site in a secure location inaccessible to entities other than the client, and rendering the render job by one or more render servers at the second rendering site.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: August 15, 2006
    Assignee: Silicon Graphics, Inc.
    Inventor: D'Arey M. Tyrrell, III
  • Patent number: 7088581
    Abstract: A modular computing system that includes an enclosure, a rack mounted inside the enclosure and a plurality of modular bricks. The modular bricks each include electronic components and are supported by the rack. The computing system further includes a floor tile supporting the enclosure. The floor tile includes a plurality of fans that exchange air with each of the modular bricks to cool the electronic components in each modular brick.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: August 8, 2006
    Assignee: Silicon Graphics, Inc.
    Inventor: Steve Modica
  • Patent number: 7089398
    Abstract: A method and system for resolving virtual addresses using a page size tag are described herein. In one embodiment, the method comprises translating a virtual memory address into physical memory address. According to the method, the translating includes producing a first page size tag and choosing an entry in a translation lookaside buffer, wherein the entry stores a second page size tag and a page frame number. The method also includes comparing the first page size tag with the second page size tag. The method also includes using the page frame number to form the physical memory address, if the first page size tag is less than or equal to the second page size tag.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: August 8, 2006
    Assignee: Silicon Graphics, Inc.
    Inventor: David Zhang
  • Publication number: 20060164414
    Abstract: A method is disclosed for culling an object database in a graphics processing system. In one embodiment, the method comprises encoding per-object parameters and culling parameters. The per-object parameters are encoded in texture format thereby creating at least one per-object texture containing the encoded per-object parameters. Next, a fragment program used in a fragment processor of the GPU is optionally updated. The updated fragment program embodies a culling operation. A polygon is then rendered, wherein the rendering step includes per-fragment operations. During the per-fragment operations, the updated fragment program is executed. The culling operation embodied therein (i) accesses the culling parameter, (ii) samples the per-object textures, and (iii) produces cull results for a set of database objects. In this fashion, the fragment processor in the GPU is leveraged to perform computationally intensive culling operations.
    Type: Application
    Filed: January 27, 2005
    Publication date: July 27, 2006
    Applicant: Silicon Graphics, Inc.
    Inventor: Paolo Farinelli
  • Publication number: 20060149904
    Abstract: A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination.
    Type: Application
    Filed: February 28, 2006
    Publication date: July 6, 2006
    Applicant: Silicon Graphics, Inc.
    Inventor: Todd Mowry
  • Patent number: 7068263
    Abstract: A compact flat panel color calibration system includes a lens prism optic able to pass a narrow, perpendicular, and uniform cone angle of incoming light to a spectrally non-selective photodetector. The calibration system also includes a microprocessor operable to determine the luminance of the display based upon the information gathered by the photodetector. A software module included in the calibration system is then operable to process the luminance information in order to adjust the flat panel display.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: June 27, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: Daniel Evanicky, Ed Granger, Joel Ingulsrud, Alice T. Meng
  • Patent number: 7069306
    Abstract: A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: June 27, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: Daniel E. Lenoski, Jeffrey S. Kuskin, William A. Huffman, Michael S Woodacre
  • Patent number: 7064755
    Abstract: The present invention provides an improved system and method for rendering shadows in a computer graphics system. Textures representing the area of influence resulting from a combination of light sources and shadow casters are pre-computed. Scenes are then rendered using the pre-computed textures. A first step entails generating sets of directions and associated pre-computed textures for each light source and shadow caster pair in a simulation frame. Next, a first scene in the simulation is rendered. During this step one or more of the pre-computed textures are used to darken the area of influence or shadow portion of the scene.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 20, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: Radomir Mech, Yair Kurzion
  • Patent number: 7062527
    Abstract: A computerized method for rendering images includes receiving a render job having at least one render frame and an associated job profile and inserting the render job into a job queue. The method also includes advancing the render job in the job queue as other render jobs are removed from the job queue, distributing the render frames via a communications medium to at least one of the plurality of render servers based at least in part on the job profile, and rendering the render frames. The method also includes forwarding the rendered render frames to a network storage system.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: June 13, 2006
    Assignee: Silicon Graphics, Inc.
    Inventor: D'Arcy M. Tyrrell, III
  • Publication number: 20060123170
    Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system is provided. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.
    Type: Application
    Filed: January 27, 2006
    Publication date: June 8, 2006
    Applicant: Silicon Graphics, Inc.
    Inventor: Shrijeet Mukherjee
  • Patent number: 7058896
    Abstract: A system, method and computer program product is provided for interactive user navigation in a real-time 3D simulation. An assembly builder permits a user to build customized physics-based assemblies for user navigation in a variety of virtual environments. These assemblies are stored in a library and are then accessed by a navigation run-time module that runs in conjunction with, or as a part of, a visual run-time application. The navigation run-time module receives high-level user goal requests via a simple and intuitive user interface, converts them into a series of tasks, and then selects the appropriate assembly or assemblies to perform each task. As a result, complex navigation may be achieved. Once selected, an assembly provides a physics-based eye-point model for user navigation. Collisions between the assembly and objects in the simulation are resolved using a real-time physics engine, thus ensuring smooth, cinematic-style eye-point modeling in addition to real-time control.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: June 6, 2006
    Assignee: Silicon Graphics, Inc.
    Inventor: David W Hughes
  • Patent number: 7058218
    Abstract: The present invention provides for a method of and apparatus for compressing and uncompressing image data. According to one embodiment of the present invention, the method of compressing a color cell comprises the steps of: defining at least four luminance levels of the color cell; generating a bitmask for the color cell, the bitmask having a plurality of entries each corresponding to a respective one of the pixels, each of the entries for storing data identifying one of the luminance levels associated with a corresponding one of the pixels; calculating a first average color of pixels associated with a first one of the luminance levels; calculating a second average color of pixels associated with a second one of the luminance levels; and storing the bitmask in association with the first average color and the second average color.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: June 6, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: Robert A. Drebin, David Wang, Christopher J. Migdal
  • Patent number: 7034837
    Abstract: Compositors are identified in a manner that defines the position of the compositor in the compositor tree. Each compositor has its own “unique compositor identifier”. Starting at the most downstream compositor, it transmits its unique compositor identifier to all upstream compositors directly coupled to it. The upstream compositors receive the unique compositor identifier from the most downstream compositor. Each of the upstream compositors appends its unique compositor identifier to the unique compositor identifier received from the most downstream compositor to produce a “compositor tree compositor identifier”. The compositor tree compositor identifier identifies both the compositor and its position in the compositor tree. This enables an application to detect the structure of the compositor tree so that the application can determine a desired tiling configuration that exploits the structure of the compositor tree.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: April 25, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: Greg Sadowski, Eric Kunze
  • Patent number: 7031420
    Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. Each of the plurality of delayed signals is compared to a reference signal to detect changes in the skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in the detected skew.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: April 18, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: Philip Nord Jenkins, Frank N. Cornett
  • Patent number: 7027072
    Abstract: A method and system for spatially compositing digital video images with a tile pattern library. Spatial compositing uses a graphics pipeline to render a portion (tile) of each overall frame of digital video images. This reduces the amount of data that each processor must act on and increases the rate at which an overall frame is rendered. Optimization of spatial compositing depends on balancing the processing load among the different pipelines. The processing load typically is a direct function of the size of a given tile and an inverse function of the rendering complexity for objects within this tile. Load balancing strives to measure these variables and adjust, from frame to frame, the number, sizes, and positions of the tiles. The cost of this approach is the necessity to communicate, in conjunction with each frame, the number, sizes, and positions of the tiles.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: April 11, 2006
    Assignee: Silicon Graphics, Inc.
    Inventor: Greg Sadowski
  • Patent number: 7016998
    Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: March 21, 2006
    Assignee: Silicon Graphics, Inc.
    Inventor: Shrijeet Mukherjee
  • Patent number: 7012614
    Abstract: The present invention provides texture roaming via dimension elevation. A degree elevated texture is used to contain level of detail (LOD) levels (or tiles) of a clip-map across a degree elevated coordinate space. For example, a three-dimensional (3D) texture is used for two-dimensional (2D) clip-mapping, a four-dimensional (4D) texture is used for 3D clip-mapping, and a 2D texture is used for one-dimensional (1D) clip-mapping. Once the levels of a clip-map are placed in an extra dimension coordinate space, the extra dimension texture coordinate value can be computed based on clip-mapping rules.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: March 14, 2006
    Assignee: Silicon Graphics, Inc.
    Inventors: Alex Chalfin, Paolo Farinelli