Abstract: A processor (100) in a distributed shared memory computer system (10) receives ownership of data and initiates an initial update to memory request. A front side bus processor interface (24) forwards the initial update to memory request to a memory directory interface unit (22). The front side processor interface (24) may receive subsequent update to memory requests for the data from processors co-located on the same local bus. Front side bus processor interface (24) maintains a most recent subsequent update to memory in a queue (102). Once the data has been updated in its home memory (17), the memory directory interface unit (22) sends a writeback acknowledge to the front side bus processor interface (24). The most recent subsequent update to memory request in the queue (102) is then forwarded by the front side bus processor interface (24) to the memory directory interface unit (24) for processing.

Abstract: A cache memory includes a plurality of data memory blocks and a code memory block. Each data memory block has a plurality of storage locations and has a particular storage location identified by a same index value. The code memory block has a plurality of code values with a particular code value being associated with the same index value. The particular code value is operable to identify which ones of the particular storage locations associated with the same index value are locked to prevent alteration of contents therein. The particular code value is also operable to identify which particular storage location has been most recently used and which particular storage location has been least recently used of the particular storage locations associated with the same index value.

Abstract: A system for prefetching information from a computer storage includes a central processing unit operable to transmit to a transfer bus a memory transfer request containing a desired memory address. The system also includes a system controller operable to receive the memory transfer request from the transfer bus and to retrieve a prefetch block of data from the computer storage in response to determining that a stream buffer local to the system controller does not contain a copy of data stored at the desired memory address. The system controller is further operable to retrieve the data from the stream buffer and communicate the data to the central processing unit in response to determining that the stream buffer contains a copy of the data stored at the desired memory address.

Abstract: A method and apparatus for processing a primitive for potential display on a display device (having a plurality of pixels) determines if the primitive intersects at least a predetermined number of pixel fragments on the display device. The predetermined number is no less than one. The method and apparatus then cull the primitive as a function of whether the primitive intersects at least the predetermined number of pixel fragments. If it is culled, the primitive is not raster processed (i.e., not subjected to raster processing, whether or not complete).

Abstract: A system, method, and computer program product for creating a sequence of computer graphics frames, using a plurality of rendering pipelines. For each frame, each rendering pipeline receives a subset of the total amount of graphics data for the particular frame. At the completion of a frame, each rendering pipeline sends a performance report to a performance monitor. The performance monitor determines whether or not there was a significant disparity in the time required by the respective rendering pipelines to render their tiles. If a disparity is detected, and if the disparity is determined to be greater than some threshold, an allocation module resizes the tiles for the next frame. This serves to balance the load across rendering pipelines for each frame.

Abstract: A modular computing system that includes an enclosure and a rack at least partially mounted within the enclosure. The modular computing system further includes a plurality of modular bricks that each include electronic components. The modular bricks are mounted in the rack and connected to the conduits in the rack. A fan is also connected to the conduits in the rack such that the rack exchanges air between the fan and each modular brick to cool the electronic components in each of the modular bricks.

Abstract: A system, method, and computer program product is presented for simulating a system of hardware components. Each component is simulated in a hardware definition language such as VERILOG. Each component is represented as a simulated device under test (DUT) that is incorporated into a simulation module. The invention synchronizes the simulation modules by issuing clock credit to each simulation module. Each simulation module can only operate when clock credit is available, and can only operate for some number of clock cycles corresponding to the value of the clock credit. Operation is said to consume the clock credit. After a simulation module has consumed its clock credit, its DUT halts. Once every simulation module has consumed its clock credit and halted, another clock credit can be issued. This allows checkpointing of the operation of each DUT and simulates parallelism of the DUTs using executable images of manageable size.

Abstract: A partitioned computer system (32) includes a plurality of node controllers (12) connected by a network (14) and partitioned into a plurality of partitioned groups (40). A requesting node controller (34) in one partitioned group (40) requests a latest copy of a line in a memory (17) in a separate partitioned group (40). A storing node controller (36) in the separate partitioned group (40) holding the latest copy of the line in its memory (17) is identified. The requesting node controller (34) transmits its request for a coherent copy of a line to the storing node controller (36). The storing node controller (36) transmits the latest copy of the line in response to the request to the requesting node controller (34) without including the requester in a sharer-tracking process.

Abstract: The present invention is directed to a method and a system for maintaining cache coherence in a distributed shared memory (DSM) multiprocessor system. The method begins with a receiving of a shared access request by a receiving node, where the receiving node is an arbitrary node having at least one main memory unit containing information desired to be accessed. Then, the method determines whether the shared access request originates from a local node or from a remote node. When the shared access request originates from a local node, the shared access request is processed as a shared access request. If the shared access request is granted, a sharing vector is generated or updated to reflect the sharing local node(s). When the shared access request originates from a remote node, the shared access request is converted to an exclusive access request and the sharing vector is replaced with a pointer to the requesting remote node. This limits the potential size of the sharing vector according to the local nodes.

Abstract: A driver operable with two power supplies, and provides, among other things, a high data communication rate, stabilized operating parameters including voltage output high, voltage output low, and on resistance, and edge rate over a wide range of variations in manufacturing process, operating voltages and temperature.

Abstract: A multiprocessor system and method includes a processing sub-system including a plurality of processors and a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store a copy of data from the processor memory system for use by a corresponding peripheral device and to delete the copy at a first time event. A directory for the processor is operable to identify the data as owned upon providing the copy to the I/O sub-system and to identify the data as unowned at a second time event.

Abstract: A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.

Abstract: A system and method for estimating interconnect delay are disclosed that include determining inductance of an interconnect. A transfer function is determined using the inductance, and two poles of the transfer function are determined. An interconnect delay is estimated using the two poles.

Abstract: A compact flat panel color calibration system includes a lens prism optic able to pass a narrow, perpendicular, and uniform cone angle of incoming light to a spectrally non-selective photodetector. The calibration system also includes a microprocessor operable to determine the luminance of the display based upon the information gathered by the photodetector. A software module included in the calibration system is then operable to process the luminance information in order to adjust the flat panel display.

Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem and operating system implementing DMAPI. Threads executing on a metadata client know when a DMAPI event is required, and generate the DMAPI event on their own initiative when necessary. A metadata server maintains DMAPI queues. If the metadata server relocates to another host, the DMAPI events in the DMAPI queues are moved transparently to users.

Abstract: A modular computer system includes at least two processing functional modules each including a processing unit adapted to process data and adapted to input/output data to other functional modules through at least two ports with each port including a plurality of data lines. At least one routing functional module is adapted to route data and adapted to input/output data to other functional modules through at least two ports with each port including a plurality of data lines. At least one input or output functional module is adapted to input or output data and adapted to input/output data to other functional modules through at least one port including a plurality of data lines. Each processing, routing and input or output functional module includes a local controller adapted to control the local operation of the associated functional module, wherein the local controller is adapted to input and output control information over control lines connected to the respective ports of its functional module.

Abstract: A computer graphics display method and system for controlling data visualization in at least one external dimension is provided which allows better querying and navigation of data in external dimension space. A data visualization is displayed in a first display window. A summary window provides summary information on data for the data visualization across one or more external dimensions. First and second controllers are displayed for controlling the variation of the data visualization in respective first and second external dimensions. A user queries the data visualization in the first and second external dimensions by selecting a point in the summary window. A user navigates through the data visualization in the first and second external dimensions by defining a path in the summary window. Grid points are also displayed in the summary window to facilitate data queries and navigation based on actual data points.

Abstract: A method and system for controlling an access to a first memory arrangement and a second memory arrangement. The method and system are adapted for controlling access to the first memory arrangement and to the second memory arrangement. A token is passed from a device associated with the first memory arrangement if the access to at least one portion of the first memory arrangement is completed, and the access to the portion of the memory arrangement is disabled. Then, upon a receipt of the token, the access to at least one portion of the second memory arrangement is enabled.

Abstract: A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers and/or for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. Since the strobe may have a delay that is unknown (due to varying distances from the driver, clock jitter, and/or other causes), it is important to re-synchronize to the internal clock, and to do so with the smallest delay possible. This synchronization is provided in a way that also eliminates potential problems due to bus-master changeover, and in a way that minimizes time-critical signal generation. One aspect provides a method and/or apparatus for reliable data capture.

Abstract: The present invention includes one embodiment of a printed circuit board assembly including a printed circuit board, a microprocessor chip, a socket and an actuator for connecting the chip to the printed circuit board, a heat sink for attachment to the top surface of the chip, and a field installable thermal interface phase change pad positioned between the heat sink and the microprocessor chip. The heat sink has an actuator access opening so that the actuator is operable with the heat sink positioned on top of the microprocessor. The connection between the chip and the heat sink is free of alignment features so that they may be separated by twisting the heat sink relative to the chip. The connection between the heat sink and the circuit board is also free of alignment features.