Patents Assigned to Silicon Graphics
  • Patent number: 6831924
    Abstract: A variable communication systems comprising a plurality of transceivers and a control circuit connected to the transceivers to configure the transceivers to operate in a bi-directional mode and a uni-directional mode at different times using different transfer methods to transfer data.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: December 14, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Frank N. Cornett, Philip N. Jenkins, Terrance L. Bowman, Joseph M. Placek, Gregory M. Thorson
  • Patent number: 6831648
    Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: December 14, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Shrijeet Mukherjee, Kanoj Sarcar, James Tornes
  • Patent number: 6831642
    Abstract: A system, method and computer program product for forming an object proxy. In one embodiment, a method forms an object proxy that approximates the geometry of an object. The method includes forming a volume that encompasses the object, forming an isosurface within the volume, adjusting the isosurface relative to a surface of the object, and pruning the isosurface to obtain the object proxy. An apparatus includes an isosurface former that forms an isosurface within a volume encompassing an object, and an isosurface shaper that adjusts the isosurface relative to the surface of the object and prunes the isosurface to obtain the object proxy.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: December 14, 2004
    Assignee: Silicon Graphics, Inc.
    Inventor: Radomir Mech
  • Publication number: 20040249904
    Abstract: A cluster of computer system nodes connected by a storage area network include two classes of nodes. The first class of nodes can act as clients or servers, while the other nodes can only be clients. The client-only nodes require much less functionality and can be more easily supported by different operating systems. To minimize the amount of data transmitted during normal operation, the server responsible for maintaining a cluster configuration database repeatedly multicasts the IP address, its incarnation number and the most recent database generation number. Each node stores this information and when a change is detected, each node can request an update of the data needed by that node. A client-only node uses the IP address of the server to connect to the server, to download the information from the cluster database required by the client-only node and to upload local disk connectivity information.
    Type: Application
    Filed: April 16, 2003
    Publication date: December 9, 2004
    Applicant: Silicon Graphics, Inc.
    Inventors: Daniel Moore, Andrew Gildfind
  • Publication number: 20040250113
    Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. At least one trusted metadata server assigns a mandatory access control label as an extended attribute of each filesystem object regardless of whether required by a client node accessing the filesystem object. The mandatory access control label indicates the sensitivity and integrity of the filesystem object and is used by the trusted metadata server(s) to control access to the filesystem object by all client nodes.
    Type: Application
    Filed: April 16, 2003
    Publication date: December 9, 2004
    Applicant: Silicon Graphics, Inc.
    Inventor: Kenneth S. Beck
  • Patent number: 6829666
    Abstract: A distributed, shared memory computer architecture that is organized into a set of functionally independent processing nodes operating in a global, shared address space. Each node has one or more local processors, local memory and includes a common communication interface for communicating with other modules within the system via a message protocol. The common communication interface provides a single high-speed communications center within each node to operatively couple the node to one or more external processing nodes, an external routing module, an input/output (I/O) module. The common communication interface that facilitates the ability to incrementally add and swap the nodes of the system without disrupting the overall computing resources of the system.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: December 7, 2004
    Assignee: Silicon Graphics, Incorporated
    Inventors: Martin M. Deneroff, Steve Dean, Timothy S. McCann, John Brennan, Dave Parry, John Mashey
  • Patent number: 6829683
    Abstract: A processor (300) in a distributed shared memory system (10) has ownership of a cache line. The processor modifies the cache line and wishes to update the home memory (17) of the cache line with the modification. The processor (300) generates a return request for routing by a processor interface (24). Meanwhile, a second processor (400) wishes to obtain ownership of the cache line and sends a read request to a memory directory (22) associated with the home memory (17) of the cache line. The memory directory (22) generates an intervention request towards the processor interface (24) corresponding to the last known location of the cache line. The processor interface (24) has now forwarded the return request to the memory directory (22) but subsequent to the read request from the second processor (400).
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: December 7, 2004
    Assignee: Silicon Graphics, Inc.
    Inventor: Jeffrey S. Kuskin
  • Patent number: 6819333
    Abstract: A system (10) for display distortion correction includes a database (18) that stores one or more pixel correction vectors (40) and one or more sub-pixel correction vectors (42). The system (10) also includes a buffer (14) that receives and stores an input image data unit (32) including a plurality of pixels. Furthermore, the system includes a system controller (12) that is coupled to the database and to the buffer. The system controller (12) generates a coarsely-corrected image data unit by mapping one or more pixels of the coarsely-corrected image data unit to corresponding pixels of the input image data unit (32) according to corresponding pixel correction vectors (40). Each pixel correction vector (40) is associated with a particular pixel of the coarsely-corrected image data unit. The system also includes an interpolation filter (16) that is coupled to the system controller (12) and the database (18).
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: November 16, 2004
    Assignee: Silicon Graphics, Inc.
    Inventor: Greg Sadowski
  • Publication number: 20040222994
    Abstract: Compositors are identified in a manner that defines the position of the compositor in the compositor tree. Each compositor has its own “unique compositor identifier”. Starting at the most downstream compositor, it transmits its unique compositor identifier to all upstream compositors directly coupled to it. The upstream compositors receive the unique compositor identifier from the most downstream compositor. Each of the upstream compositors appends its unique compositor identifier to the unique compositor identifier received from the most downstream compositor to produce a “compositor tree compositor identifier”. The compositor tree compositor identifier identifies both the compositor and its position in the compositor tree. This enables an application to detect the structure of the compositor tree so that the application can determine a desired tiling configuration that exploits the structure of the compositor tree.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 11, 2004
    Applicant: Silicon Graphics, Inc.
    Inventors: Greg Sadowski, Eric Kunze
  • Patent number: 6816145
    Abstract: A large area wide aspect ratio flat panel display having high resolution for high information content display. The present invention includes a liquid crystal flat panel display monitor having a wide aspect ratio. In one embodiment, the wide aspect ratio is substantially 1.6:1, having 1,600 pixels across the horizontal and 1,024 across the vertical. In this embodiment, the present invention is an SXGA-wide flat panel display monitor having high resolution for high information content display. The monitor of the present invention is particularly well suited for the display of text, graphics and other types of still and/or motion audio/visual works. The wide aspect ratio allows the display of multiple pages, side-by-side, thereby facilitating certain tasks such as desktop publishing, presentation of interactive windows, presentation of menus, chart viewing, digital photography, tactical military displays and weather and aircraft monitoring.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: November 9, 2004
    Assignee: Silicon Graphics, Inc.
    Inventor: Daniel E. Evanicky
  • Patent number: 6816947
    Abstract: A memory access arbitration scheme is provided where transactions to a Shared memory are stored in an arbitration queue. Prior to arbitration, the transactions are compared against the contents of cache memory, to determine which transactions will hit in cache, which will miss and which will be victims. Also prior to arbitration, the entries in the arbitration queue are grouped according to a transaction parameter, such as DRAM bank, Write to Bank, Read to Bank, etc. Arbitration is the performed among those groups which are ready for service. From the group winning arbitration, the oldest transaction is selected for servicing. Preferably, a collapsible queuing structure and method is used, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: November 9, 2004
    Assignee: Silicon Graphics, Inc.
    Inventor: William A. Huffman
  • Patent number: 6813151
    Abstract: A computer enclosure and method for manufacture include a computer housing and an outer layer, the housing having an inner surface and an outer surface, the outer layer having a first surface and a second surface, wherein the first surface of the outer layer is coupled to the outer surface of the housing and covers a substantial portion of the outer surface, and the second surface of the outer layer has a graphic design applied thereto.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: November 2, 2004
    Assignee: Silicon Graphics, Inc.
    Inventor: Cullen P. Vane
  • Patent number: 6813739
    Abstract: A can test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: November 2, 2004
    Assignee: Silicon Graphics, Inc.
    Inventor: Louis C. Grannis, III
  • Patent number: 6813599
    Abstract: A method for efficiently simulating memory structures of a sequential circuit for design verification of the sequential circuit. The method is implemented by an computer system having a processor coupled to a memory via a bus, the memory storing computer readable code which when executed by the processor cause the computer system to perform the steps of the memory structure simulation method. The method includes accessing a netlist description of a sequential circuit, wherein the description is for realizing the sequential circuit in a physical form. Memory elements included within the description are identified. For these memory elements, inputs to the memory elements and outputs from the memory elements are identified. Using this information, the memory elements are grouped into at least one group of functionally related memory elements. Subsequently, the memory elements of the one or more groups are collectively addressed as a group.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: November 2, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Thomas Court, Abdulla Bataineh, Dennis Kuba
  • Patent number: 6809739
    Abstract: A variable number of textures are blended together using a single texture as a mask. At least four textures are received. Masks are extracted from one of the received textures and used to blend together the remaining textures. In an embodiment, N masks are extracted from a single texture and used to blend N+1 additional textures. In this embodiment, two of the N+1 textures are initially blended together in accordance with one of the N masks to form an image. Another texture of the N+1 textures is then blended with the image in accordance with another one of the N masks. This iterative blending process continues until all of the N+1 textures have been blended together. In another embodiment, N textures are blended together by multiplying each of the N textures by one of the N masks and adding together the results of the N multiplications.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: October 26, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Paolo Farinelli, Angus M. Dorbie
  • Patent number: 6809733
    Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: October 26, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: Shrijeet Mukherjee, Kanoj Sarcar, James Tornes
  • Publication number: 20040210673
    Abstract: A cluster of computer system nodes connected by a storage area network transmit messages using a messaging protocol having multiple layers. The storage area network supports computer system nodes running different operating systems on different endian processors. A heartbeat signal is transmitted in a common wire format over the lowest level of the messaging protocol; however other messages between the nodes may be transmitted in a format different from the common wire format. The node receiving a message is responsible for converting the format as necessary in a layer just above the layer of the messaging protocol handling heartbeat signals. However, conversion may be performed by the sending node if the sending node knows the format used by the receiving node.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Applicant: Silicon Graphics, Inc.
    Inventors: Mark Cruciani, Kenneth S. Beck
  • Publication number: 20040210656
    Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network connected to the nodes by switches, such as Fibre Channel switches. When a node fails to respond to other members of a cluster, the node is prevented from accessing storage devices shared by the nodes in the cluster by disabling port(s) on the switches connected to the failed node. The ports to be disabled are identified in a cluster configuration database that is updated as each node joins the cluster. Commands to disable port(s) of a switch may be transmitted to the switch in a telnet session from the node maintaining the cluster configuration database.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Applicant: Silicon Graphics, Inc.
    Inventors: Kenneth S. Beck, Mark J. Goodwin
  • Publication number: 20040207599
    Abstract: The present invention is a system that allows a number of 3D volumetric display or output configurations, such as dome, cubical and cylindrical volumetric displays, to interact with a number of different input configurations, such as a three-dimensional position sensing system having a volume sensing field, a planar position sensing system having a digitizing tablet, and a non-planar position sensing system having a sensing grid formed on a dome. The user interacts via the input configurations, such as by moving a digitizing stylus on the sensing grid formed on the dome enclosure surface. This interaction affects the content of the volumetric display by mapping positions and corresponding vectors of the stylus to a moving cursor within the 3D display space of the volumetric display that is offset from a tip of the stylus along the vector.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 21, 2004
    Applicant: Silicon Graphics, Inc.
    Inventors: Gordon Paul Kurtenbach, George William Fitzmaurice, Ravin Balakrishnan
  • Publication number: 20040210852
    Abstract: The present invention is directed to a two-handed input control system that dynamically changes an input-to-object mapping for mapping movement of a graphical object on a display of a virtual scene as the viewpoint of the virtual scene changes. As input to the system for changing the position of the graphical object occurs, the mapping is revised to reflect changes in the viewpoint so that the object moves as inherently expected. That is, changes to the viewpoint change the mapping so that a correspondence between the viewpoint and the input space is always maintained. During movement of the object a screen cursor is visually suppressed so that the movement of the graphical object and the screen cursor do not split the attention of the user. The screen cursor is always maintained within the visual display region of the virtual scene even when the object moves out of the visual display region by moving the cursor to a center of the screen when it reaches an edge of the screen.
    Type: Application
    Filed: May 10, 2004
    Publication date: October 21, 2004
    Applicant: Silicon Graphics, Inc.
    Inventors: Ravin Balakrishnan, Gordon Kurtenbach