Abstract: A system and method for providing a graphical user interface (GUI) for maximized user performance and system efficiency. The GUI utilizes variable-transparency to merge images (or layers) of objects onto a graphical display. For example, "see through" objects (such as menus, tool palettes, windows, dialogue boxes, or screens) are superimposed over similar objects or different background content (such as text, wire-frame or line art images, or solid images). A critical factor in the usability of variably-transparent GUI is the effect of visual interference on user performance. That is, the interaction between superimposed objects of varying types measurably alters performance to unacceptable levels in terms of user selection error rates and response times. The present invention provides a system and method of using optimal threshold transparency levels for user performance optimization.

Abstract: A memory system that includes switches for controlling data transfer that are disposed on the motherboard. The switches are selectively coupled to a controller and to connector receptacles that are adapted to receive a memory module. The memory system also includes resistors that are disposed on the motherboard for terminating data signals. In one embodiment, memory modules are accessed in pairs. That is, the data switches are used to control the flow of data signals such that data signals only flow to one pair of memory modules at any particular time. In one embodiment, the memory system of the present invention includes eight memory modules that use DDR SDRAM memory components. When 8 Mbit, 16 Mbit, 32 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 128 megabytes (Mbytes) to 1 gigabyte (Gbyte).

Abstract: A system, method and computer program product for distributing page caches among memory objects and, in a DSM system, among memories in the DSM system. The system, method and computer program product provides a separate page cache for each memory object. Each separate page cache associates page frame data structures that represent pages of memory that store a portion of an associated memory object. A separate mutual exclusion mechanism is provided for each page cache for protecting the integrity of the page caches during page cache operations. Page cache operations, such as adding and deleting page frame data structures, checking and updating state information in page frame data objects, and identifying page frame data objects that correspond to particular memory objects or memory object logical offsets, can be performed for different memory objects in parallel.

Abstract: A system that includes a flat panel display that can change three-dimensional orientation in a continuous way, such as when the display is horizontally rotated on a turntable. Position or orientation of the display relative to a reference orientation is sensed by orientation sensors coupled to the display. A computer compares the orientation of the display to a fixed reference orientation. When the orientation of the display has changed from the reference, the computer maps the orientation of a user interface onto the display in such a way as to maintain the same orientation of the interface with respect to the reference. User input through an overlaid input device correlates to the oriented user interface. In this way if the display is rotated into, for example, a sideways or upside-down orientation, the user interface elements will still be displayed in a normal upright orientation for the user and the user inputs in a normal manner.

Abstract: An input system for controlling the position or motion of a cursor, three dimensions that uses x, z position for inputting two coordinates and tilt in a plane (x-y or z-y) to input a third (and possibly a fourth coordinate). The invention is moved about on a surface for inputting two of the dimensions and tilted to input the third. The amount or degree of tilt and the direction of tilt controls the input of the third dimension. The base of the hand held device is curved so that the device can be tilted even while it is moved in two dimensions along the surface of the tablet. Tilting can be along two orthogonal axes allowing the device to input four coordinates if desired. The coil can also have switched resistors controlled by mouse buttons connected to it which the tablet can sense being activated to allow clutching and selection operations like those of a conventional mouse.

Abstract: A system, method and computer program product for reverse mapping a page of memory to one or more data structure references, such as page table entries, that reference the page of memory. A number m of fields of a page frame data structure are reserved for storing reverse mapping data for a page of memory. Each reserved field can store a reverse map entry for pointing to a data structure reference, such as a page table entry, that references the page of memory that is represented by the page frame data structure. Where a number n of references to the page of memory is greater than the number m of reserved fields, a reverse map table is generated for storing additional reverse map entries. When a reverse map table is generated, one of the reverse map entries in one of the reserved fields of the page frame data structure is moved to the reverse map table. A pointer to the reverse map table is placed in the now-vacant reserved field.

Abstract: A system, method and computer program product for virtual memory support for TLBs with multiple page sizes that require only minor revisions to existing operating system code and remains compatible with existing applications. The virtual memory support provided herein is transparent to many existing operating system procedures and application programs. Various page sizes such as 4 KB, 64 KB, 256 KB, 1 MB, 4 MB and 16 MB page sizes can be used by application programs and each process can use multiple page sizes. Base page sized PTEs and data structures associated with physical pages (PFDATs) are maintained. Maintaining PFDATs and PTEs at a base page level facilitates upgrading and downgrading of memory pages. In addition, different processes can have different views of the same data. Support is provided for upgrading and downgrading memory pages. Examples of operating system methods that can be used for virtual memory support for multiple page sized TLBs are provided herein.

Abstract: A method, system, and computer program product provides data visualization which optimizes visualization of and navigation through hierarchies. A partial hierarchy is generated and displayed. The partial hierarchy consists of a number levels at least equal to a predetermined depth and less than a total number of levels included in a corresponding complete hierarchy. Parent nodes in the bottom level of the partial hierarchy have segments of connection lines extending toward child nodes not included in the partial hierarchy. A user is permitted to mark selected nodes or locations in a displayed partial hierarchy. Partial hierarchies are generated and stored in a cache or generated on-the-fly. Each partial hierarchy ends at a progressively deeper level. An interpolator interpolates a partial hierarchy layout by interpolating corresponding nodes in two partial hierarchies. A hierarchy manager manages partial hierarchies in response to requests from a viewer to move a camera to camera positions.

Abstract: A method, system, and computer program product are provided for increasing interpolation bit precision using multi-channel texture mapping. According to the present invention, pixels are separated into respective groups of data segments in multiple texture channels. The groups of data segments in each texture channel are interpolated in parallel to obtain an interpolated pixel value for each texture channel. The interpolated pixel value for each texture channel for a sample is stored in a frame buffer. An accumulation operation, such as, blending, is used to accumulate interpolated pixel values for each texture channel for a number of samples in the frame buffer. In one example, interpolation according to the present invention is used in computer tomography and volume rendering using texture mapping. In another example of the present invention, interpolation is used in computer graphics processing using texture mapping.

Abstract: A system and method for maintaining consistency between translational look-aside buffers (TLB) and page tables. A TLB has a TLB table for storing a list of virtual memory address-to-physical memory address translations, or page table entries (PTES) and a hardware-based controller for invalidating a translation that is stored in the TLB table when a corresponding page table entry changes. The TLB table includes a virtual memory (VM) page tag and a page table entry address tag for indexing the list of translations The VM page tag can be searched for VM pages that are referenced by a process. If a referenced VM page is found, an associated physical address is retrieved for use by the processor. The TLB controller includes a snooping controller for snooping a cache-memory interconnect for activity that affects PTEs. The page table entry address tag can be searched by a search engine in the TLB controller for snooped page table entry addresses.

Abstract: A computer system provides dynamic memory allocation for graphics. The computer system includes a memory controller, a unified system memory, and memory clients each having access to the system memory via the memory controller. Memory clients can include a graphics rendering engine, a CPU, an image processor, a data compression/expansion device, an input/output device, a graphics back end device. The computer system provides read/write access to the unified system memory, through the memory controller, for each of the memory clients. Translation hardware is included for mapping virtual addresses of pixel buffers to physical memory locations in the unified system memory. Pixel buffers are dynamically allocated as tiles of physically contiguous memory. Translation hardware is implemented in each of the computational devices, which are included as memory clients in the computer system, including primarily the rendering engine.

Abstract: A method of a computer graphics system accelerates minified texture cache access by determining a starting address of a texture in s and t coordinates and a level of detail (LOD) of the texture. The texture includes tiles of texels stored in a memory. Then, the method of the present invention reads a succession of each of the tiles of the texture from the memory based on the starting address of a first of the succession of tiles. For each tile in the succession of tiles, each texel in the succession of texels being read is a distance of 2.sup.LOD texels from a previous texel in the succession of texels.

Abstract: A high-precision multi-channel blending operation replaces a single pass blending operation to overcome distortions resulting from an insufficient number of bits available per pixel in a hardware frame buffer. A desired frame buffer configuration, with a fewer number of channels, and a larger number of bits available per channel than available for a single pass blending operation, is specified and allocated in memory. The same, fewer number of channels from a destination image are written into the frame buffer. The frame buffer is configured for blending, and the same, fewer number of channels from the source image are blended into the frame buffer. The contents of the frame buffer is written into a memory location. The above steps are repeated, until all of the channels have been blended and written into different parts of memory. The channel information from the memory locations are combined to form an image having a user-desired bit resolution.

Abstract: A method and arrangement for dynamically generating computer displayable graphics for the World Wide Web is provided. Upon receiving a request from an end user over the web, a server executes a program stored in its memory to retrieve data from a selected data source such as a continuously updated data base. Next, the server executes a second program stored in its memory using the data retrieved as input to generate computer graphics. The second program is written in a flexible and easy to use general purpose graphics generating programming language. The server sends the computer graphics generated over the World Wide Web to the end user who requests it.

Abstract: A method and system for emulating on-line accessing of information in an off-line environment. In one embodiment, information initially configured to be displayed via an on-line connection is stored onto a plurality of portable storage media. The portable storage media is adapted to be used by an end-user in an off-line environment. Moreover, in the present embodiment, the information is arranged on the plurality of storage media such that off-line accessing of the information emulates on-line accessing of the information. That is, in the present invention, information is presented to an off-line end-user in a manner which emulates the manner in which the same information would have been presented to the end-user in an on-line environment. In one embodiment, the present invention stores Web site information onto the plurality of portable storage media.

Abstract: In a computer, a graphics system and process for generating a multisample image coverage mask comprising a constant number of samples. The mask covers an array of pixels with each pixel containing a number of samples. The samples are associated with information regarding the image which is used by the computer graphics system to render the image on a pixel. The samples utilized in creating the mask are those closest to the center of an image.

Abstract: A ball grid array (BGA) land pattern. In the present invention, a capture pad is disposed on a substrate. The capture pad is electrically coupled to a via which is formed into the substrate. A substantially rectangularly-shaped landing pad is also disposed on the substrate proximate to the capture pad. The substantially rectangularly-shaped landing pad is electrically coupled to the capture pad. In one embodiment, an electrically conductive connecting region electrically connects the substantially rectangularly-shaped landing pad to the capture pad. More specifically, the electrically conductive connecting region has a first end coupled to the capture pad and a second end coupled to the substantially rectangularly-shaped landing pad.

Abstract: A process and apparatus for quantum acceleration of a conventional computer by coupling a few quantum devices to the conventional computer. Initially, a first, second, and third maximally entangled qubit are prepared in a Greenberger-Horne-Zeilinger state. A fourth qubit is prepared in a perfect superposition of states which is unentangled from the three qubits. The second qubit is then measured and its measured value is input to the conventional computer. The conventional computer operates on this measured input value and performs an inverse oracle function. The second qubit is modified according to the output from the conventional computer. This modified qubit is used as one of two control inputs for controlling a quantum gate. The other control input is the fourth qubit. The quantum gate phase inverts the third qubit according to the two control inputs. A measurement of the complement of the first qubit is taken in order to produce the necessary quantum interference of the third qubit.