Patents Assigned to Silicon Graphics
  • Patent number: 6081829
    Abstract: A general purpose system and method for associating annotations, modifications, or other information with a web-viewable document is disclosed. An embodiment of the system and method includes the use of a "redirector." A user attempting to access a document at a particular web address, sends a request to view the document to that address. The request is intercepted by the redirector which, in turn, requests the document on behalf of the user. The redirector modifies the document and returns the modified document for viewing by the user. The modifications may include, for example, various comments or annotations to the original web-viewable document. According to the invention, such customized documents may be presented to the user without modification of commercially available browser and/or server software.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: June 27, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: Ashmeet S. Sidana
  • Patent number: 6078331
    Abstract: A process for efficiently drawing subdivision surfaces. The present invention operates within a computer system for visually displaying 3 dimensional (3D) surfaces on a display. The present invention pulls polygons from a polygon mesh of a 3D surface. The polygons are stored into a 2 dimensional array such that the vertices of the polygons occupy nodes of the 2 dimensional array and are readily accessed. The polygons are subsequently divided into a plurality of resulting polygons. The resulting polygons are then sent to a graphics pipeline, wherein the graphics pipeline renders the resulting polygons into a 3D image on the computer display.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: June 20, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Kari Antero Pulli, Mark Gordon Segal
  • Patent number: 6078332
    Abstract: The present invention includes a method and system for providing real-time realistic lighting to graphics objects within a computer controlled graphics display system utilizing 3D texture mapped light values. The present invention generates and utilizes a 3D texture map indicating light intensity values with a predefined 3D graphics region. In generating the 3D texture map light values, the present invention selects a point (x, y, z) within the 3D graphics region that is to be displayed on a display screen and determines which light sources contribute to the illumination of the point. Based on the light sources that do contribute to the illumination of the point, the original intensity of each light source and its distance from the point are determined. Based on a determined distance formula, the attenuation of each light source is determined with respect to the point. Based on the attenuation and intensity data, the light intensity value of the point is determined.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: June 20, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: Chikai J. Ohazama
  • Patent number: 6077311
    Abstract: A method and apparatus for marking a region of source code within a program unit and extracting an executable version of this marked region of code. The executable version has a initialized program state equivalent to that of the original source code when the original source code entered the region. The method and apparatus remove as much source code as possible from the original source code while retaining enough code to enable the extracted region execute (replay) in a manner identical to the execution of the program region in the context of the original system.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: June 20, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Walter D. Lichtenstein, Rune Dahl, Ross Towle
  • Patent number: 6078515
    Abstract: A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: June 20, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Michael J. K. Nielsen, Brian Kindle, Linda S. Gardner, Zahid S. Hussain
  • Patent number: 6075906
    Abstract: A system and method for scaling image streams that use motion vectors is disclosed. The system combines an error term with a predicted term in order to produce a display value. The system operates on image components represented in the spatial and frequency domains. The system processes motion vectors in the spatial domain. The motion vectors are scaled. The integral part of the scaled motion vector addresses a framestore. The fractional portion of the scaled motion vector is input to a nonlinear filter which determines the value of image components for a location that does not correspond with an image location in the framestore. The output of the nonlinear filter comprises the predicted terms. Data in the frequency domain is processed more efficiently by reducing the size of a block of data by appropriate filtering. The resulting data is transformed to the spatial domain.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: June 13, 2000
    Assignee: Silicon Graphics Inc.
    Inventors: Stephen C. Fenwick, Timothy J. Van Hook, Gregory Humpreys Efland
  • Patent number: 6075543
    Abstract: A system and method for managing multiple frame buffers. The system includes multiple frame buffers, and thus reduces the risk of dropped frames. The system controls and bounds render-to-display latency, and provides an application friendly and effective interface to the frame buffers. The system operates by estimating a latency of a frame that is yet to be rendered. The system determines whether the latency is greater than a target latency. If the latency is greater than the target latency, then the system blocks the application that is responsible for rendering the frame before rendering of the frame commences. As a result, render-to-display latency is bounded to the target latency. The system addresses the naming issue by providing the application with access to only the front buffer and the back buffer. In particular, the present system maintains a queue of one or more frame buffers. The newest frame buffer appended to the queue is considered to be the front buffer.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: June 13, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: Kurt Barton Akeley
  • Patent number: 6072500
    Abstract: An image processing system is described that receives polygonal image data at the direction of a processor and develops antialiased image data for display on a raster scanned display. In particular, the image system includes a scan convertor for converting the polygonal image data into pixel data, which includes pixel screen coordinates and at least one color value for each polygon covered pixel of the pixel data and a supersample coverage mask indicating an extent of polygon coverage within each polygon covered pixel. The image system also includes a raster system having at least one image processor for receiving the pixel data for each pixel, for developing a region mask based on the supersample coverage mask, and for storing the color value in association with the region mask as anitialiased display data in an image memory in communication with the image processor based on the pixel screen coordinates.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: June 6, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: James L. Foran, Mark M. Leather
  • Patent number: 6072491
    Abstract: A system and computer-based method for permitting a computer system to access a network location using a browser application by activating a desktop icon. The system comprises a first computer readable program code means for causing the computer system to display a desktop icon associated with a file containing a network address corresponding to the network location. When the desktop icon is activated, a second computer usable program code means causes the computer to launch an instance of a browser application or a new window for a currently executing browser application and a third computer usable program code means causes the computer system to pass the network address to the browser application, thereby accessing the network location.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: June 6, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: Steven J. Yohanan
  • Patent number: 6073090
    Abstract: A system and method for independently configuring international location and language in a computer system generates composite locales for user-selected location and language combinations whenever a user-selected location and language combination is unsupported by default locales. The system includes a location format retrieval element for retrieving location-specific formatting data and a language format retrieval element for retrieving language-specific formatting data. A composite locale generator combines retrieved location-specific and language-specific data to generate a composite locale. In a preferred embodiment, a composite locale is generated from default locales. The location format retrieval element retrieves location-specific formatting data from a first default locale and the language format retrieval element retrieves language-specific formatting data from a second default locale.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: June 6, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Erik Fortune, Gianni Mariani
  • Patent number: 6070002
    Abstract: A computer system having a shared system memory, and system software in the computer system, are described herein. One or more user applications execute in the computer system. The computer system has a general purpose, shared system memory that is used for all processing, including video input/output operations and image conversion operations. The computer system also has a multimedia access and control module (MACM), which is the input/output interface between the computer system and the external world. In operation, the MACM receives, at one of its video input ports, video data comprising a video image (such as a frame or a field). The MACM stores the video image in a first buffer contained in a first buffer pool of the system memory. The first buffer pool was previously created by a user application. The user application previously associated the first buffer pool with the MACM's video input port. A video imaging and compression module (VICM) performs image conversion operations.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: May 30, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Bent Hagemark, Angela Lai, Kevin Meier, Jonathan Wesener, Brian Beach, John Wiltse Carpenter
  • Patent number: 6067634
    Abstract: A system for recovering resources, wherein the system includes a plurality of allocating services that each allocate resources to clients and a resource audit service in communication with each of the plurality of allocating services. When one of the plurality of allocating services allocates a resource to a client, the one of the plurality of allocating services sends a registration to the resource audit service identifying the client as a recipient of the resource. The resource audit service monitors status of the clients thereby freeing the plurality of allocating services from individually monitoring the status of the clients to which resources have been allocated. When one of the clients fails, the resource audit service sends a failure notification to each of the plurality of allocating services that have allocated a resource to the failed client, thereby allowing each of the plurality of allocating services to recover the resource that had been allocated to the failed client.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: May 23, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: Michael N. Nelson
  • Patent number: 6065084
    Abstract: A programmable packer and unpacker with dither support is disclosed. In one embodiment of the invention, a packer packs a plurality of bits of a first bus to a lesser plurality of bits of a second bus according to one of a plurality of different packing modes. In another embodiment, an unpacker unpacks a plurality of bits of a first bus from a lesser plurality of bits of a second bus according to one of the plurality of different packing modes. The packer comprises a plurality of multiplexers and a microstore in an exemplary embodiment. The microstore controls the select bits for the plurality of multiplexers, and is programmed in accordance with one of the different packing modes. The multiplexers determine which bits from the input bus will be transferred to the output bus. Because the microstore can be reprogrammed, the packer is programmable and thus universal.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: May 16, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Tony Chatzigianis, Scott Kenneth Pritchett
  • Patent number: 6059839
    Abstract: In a compiler for processing a software program and generating machine executable code, a method for optimizing a plurality of variables that have their addresses taken. The method is comprised of the steps of processing source code in a front end of the compiler, to determine a plurality of variables that have their addresses taken. The compiler then analyzes local calls for the plurality of variable that have their addresses taken and determines which local variables may be safely optimized. The compiler then analyzes global calls for the plurality of variables that have their addresses taken and determines which global variables may be safely optimized. The compiler then optimizes the code by moving the code containing local variables and global variables outside of the code loops in the software program.
    Type: Grant
    Filed: January 9, 1997
    Date of Patent: May 9, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: James C. Dehnert, Wingshun Wilson Ho, Seema Hiranandani
  • Patent number: 6061104
    Abstract: A display assembly that includes a flat panel display and a display stand. A hinge that attaches to the housing of the display provides for tilt adjustment. The display stand includes two rails that attach to a base and a sliding frame that is coupled to the hinge. The two rails support the sliding frame such that the sliding frame can move up and down along the two rails. A rotary dampener dampens downward movement of the sliding frame. The display stand also includes a latching mechanism that selectively latches the sliding frame to one of the rails. The latching mechanism includes a handle that can be manually operated so as to selectively engage and disengage the latching mechanism. Movement of the handle of the latching mechanism releases the latching mechanism. The display can then be moved up or down as desired to accommodate the needs of a particular user. Once the display is positioned as desired, the release of the handle operates to engage the latching mechanism.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: May 9, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Daniel E. Evanicky, Thomas Mabry, Carl Engelbrecht
  • Patent number: 6057850
    Abstract: A method and apparatus for expeditiously rendering realistic bumpy self-shadowed textured computer graphics is provide. Illuminated texture images of an object are obtained and stored in a data base as texture maps. These illuminated texture images are superimposed on top of each other and blended according to their weighted illumination contributions from the light sources to create a blended texture map. This blended texture map is then mapped to the desired surface of the geometric object.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: May 2, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: John J. Kichury
  • Patent number: 6055579
    Abstract: A system for synchronization of data processing in a data processing system including multiple command queues is disclosed. The disclosed data processing system includes one or more processing engines associated with one or more command queues. The use of multiple command queues supports multiple priority levels, such that commands in higher priority queues may preempt commands in lower priority queues. Data processing is synchronized by queue commands that allow a processing engine to queue commands on the command queue of any processing engine in the data processing system, including its own. Multiple data dependencies are resolved by conditional queue commands and event counters that queue a command only when all of the conditions precedent to execution of a particular data processing command are satisfied. The hardware queuing of the disclosed invention advantageously synchronizes data processing with minimal software supervision and with minimal latency.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: April 25, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Girish Kumar Goyal, Robert Anthony William, Michael Ken Minakami, David Allen Lockett, Tarik Isani, Mark Paul von Gnechten
  • Patent number: 6049866
    Abstract: A method and a system for fast user mode cache synchronization. The present invention is implemented on a computer system having a instruction cache. The system of the present invention detects a simulated instruction from a process running on the computer system while the process is running in a user mode. The simulated instruction causes an error exception and the operating system traps the error. The kernel then interprets the simulated instruction is then as an instruction cache synchronization instruction. The instruction cache synchronization instruction is executed and the program counter is incremented. The present invention then returns to the process in user mode. During instruction execution, preloaded registers that contain a starting address and an ending address, defining an address range, are read. The entries of the instruction cache are read and those entries falling within the address range are marked as invalid to maintain instruction cache coherency.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: April 11, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: William J. Earl
  • Patent number: 6049476
    Abstract: A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: April 11, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: James P. Laudon, Daniel E. Lenoski, John Manton, Michael E. Anderson
  • Patent number: 6044424
    Abstract: A system and method for minimizing disruption of operating power in a high-availability computer as new power supplies are hot-inserted. In the preferred embodiment, the high-availability computer includes a plurality hot-plug power supplies, a logic circuit system, and a power distribution system for distributing operating power from the power supplies to the logic circuit system. Preferably, the output capacitance of each power supply is significantly less than the total capacitance of the logic circuit system and the power distribution system, such that, as each power supply is hot-inserted into the computer, only a minute amount of electric charges will be transferred from the power distribution system and the logic circuit system to the power supply. As a small amount of charge transfer would generate only a small voltage drop, any glitch produced by hot-insertion would be significantly reduced.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: March 28, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: Dilip Amin