Abstract: A three dimensional selection entity for interactively selecting among the displayed objects represented in three-dimensional space. A user selects one of several three-dimensional selection entities provided in accordance with the present invention. The user manipulates the three-dimensional selection entity to designate the three-dimensional space of interest. The objects are deemed to be selected depending on whether the selection entity encompasses at least a portion of the object.

Abstract: A system and method of antialiasing edges of a texture that is being projected onto a polygon surface are described. The system operates by determining an initial opacity value of a pixel of the polygon surface as mapped into the texture, and then adjusting the initial opacity value so as to achieve a single pixel wide projected texture edge. This adjustment is performed by determining whether the initial opacity value is less than a threshold, where the threshold represents a desired alpha value of pixels along a projected texture edge. If the initial opacity value is less than the threshold, then a new opacity value of the pixel is set equal to a value denoting full transparency. If, instead, the initial opacity value is greater than the threshold, then a new opacity value of the pixel is set equal to a value denoting full opacity.

Abstract: A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilitates the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.

Abstract: An indexing method for allowing a viewer to control the mode of delivery of program material. By mapping from time to data position, data delivery can begin at any selected time in the program material. The indexing method also provides for controlling data delivery to begin at the beginning of a frame of data. A synchronizing method is provided to minimize a time offset between audio and video data, particularly in environments using groups of pictures.

Abstract: A temporal data control system that uses a hand held, mobile scrubwheel that includes two position indicators and an activation switch. As a user moves the scrubwheel about on a surface of a position sensing tablet a computer controls the movement of a cursor on a display. The computer also displays one or more temporal sequences, such as video sequences, on the display. Movement of the scrubwheel is detected by the computer allowing the user to position the cursor on a sequence to be controlled which the computer interprets as selecting the sequence. The computer detects rotation of the scrubwheel and controls the forward and backward motion (and speed) of the sequence responsive to the rotation. By moving the device to another location on the surface the user can select another sequence to control. The user can "point-and-scrub" temporal sequences.

Abstract: A method, system, and computer program product are provided for profiling virtual memory accesses by one or more threads. A virtual memory access thread profiling tool includes a histogram generator and a thread placement file generator. The histogram generator generates a histogram that indicates the relative frequency at which virtual memory addresses are accessed by each program thread. To generate the histogram, the histogram generator runs and interrupts each program thread to collect samples. When an interrupt is issued, a program counter is returned. A valid load or store instruction is determined for a thread in assembly code identified by the returned program counter. In one example, to determine a valid load or store instruction, the histogram generator walks forward or backward through the assembly code identified by the returned program counter until a valid load or store instruction is reached. A virtual memory address corresponding to a valid load or store instruction is then read.

Abstract: An input/output flow control system for a processor system having an input/output request source (e.g., a processor) and a plurality of input/output request targets (e.g., I/O busses) uses a NACKing (negatively acknowledging) scheme to prevent a common I/O path from becoming blocked due to the blockage of one or more I/O buses. The system includes a flow controller associated with each of the targets for receiving input/output requests from the source, for accepting (ACKing) a request if the intended target can accept the request, and for NACKing a request if the intended target cannot accept the request. The system also includes a processor or source interface for resending the NACKed requests to the intended target and for cooperating with the flow controller so that the NACKed requests are accepted by the flow controller in the proper order.

Abstract: An integral actuator mounts to a printed circuit board and effects connection of the printed circuit board to an external device, such as a motherboard, from a remote position outside of the printed circuit board. The actuator includes a platform affixed to the printed circuit board, a plunger (with a handle) slidably attached to the platform, and a cam slidably and rotatably attached to the plunger. When a customer pushes the plunger handle (which extends outside the bulkhead assembly of the printed circuit board) the plunger slides inward, causing the cam to rotate. This rotation of the cam pushes connector pins into the motherboard (for an electrical connection) and attaches the printed circuit board to the motherboard. The printed circuit board can also be unattached from the motherboard if the customer pulls the plunger handle, where the cam and the plunger move in a reversed manner. In a preferred embodiment, an actuator structure is provided that attaches to the back of the printed circuit board.

Abstract: In a microprocessor system utilizing a cache memory, an uncached store buffer is provided for efficiently providing uncached store data and uncached store addresses to a multiplexed system interface address/data bus. The uncached store buffer includes detector means, coupled to receive uncached store addresses, for detecting on-the-fly successive uncached store addresses which are identical, and for detecting on-the-fly successive uncached store addresses which are sequential. The uncached store buffer further includes an address buffer, coupled to receive and store a plurality of the uncached store addresses, and control logic, coupled to an output of the detector means, having a control signal. A data buffer, coupled to receive uncached store data, is further provided to store a plurality of blocks of the uncached store data. The uncached store data is arranged in the data buffer without gaps under the control of the control signal.

Abstract: A system and method are provided for scheduling an event subject to the availability of requested participants. A server application (16) receives event information submitted by a scheduler using a client application (12) to access an event definition page (50). The event information provides one or more options for scheduling an event and lists a plurality of requested participants. Responsive to receiving the event information, the server application (16) creates an event reply page (60) and an event confirmation page (70). The server application (16) then creates and sends an electronic mail message to each requested participant to provide information about the one or more options and a link to the event reply page (60). The server application (16) also creates and sends a message to the scheduler to provide a link to the event confirmation page (70).

Abstract: The present invention is a system, method, and computer program product for dynamically sizing a hash table when the average number of records per bucket in the hash table exceeds a maximum average number of records per bucket. In one embodiment, the hash table employs a modulo hashing function. In a second embodiment, the number of buckets is grown by a multiple of the previous number of buckets and records are re-hashed using a lazy re-hashing modulo algorithm that re-hashes records in a hash bucket only when those records are searched. In the second embodiment, when a hash table is re-sized, each new bucket is provided with a logical back pointer, or index, to a pre-existing bucket that potentially contains records that belong in the new bucket. When a search is directed at a new bucket, the logical back pointer, or index, directs the search to a pre-existing bucket. When a search of a pre-existing bucket finds a data record that belongs in a new bucket, the record is moved to the new bucket.

Abstract: A data record transformation that computes histograms and aggregations quickly for an incoming record stream. The data record transformation computes histograms and aggregations in one-step, thereby, avoiding the creation of a large intermediate result. The data record transformation operates in a streaming fashion on each record in an incoming record stream. Little memory is required to operate on one record or a few records at a time. According to a first embodiment, a method, system, and computer program product for transforming sorted data records is provided. A data transformation unit includes a binning module and a histogram aggregation module. The histogram aggregation module processes each binned and sorted record to form an aggregate record in a histogram format in one step. Data received in each incoming binned and sorted record is expanded and accumulated in an aggregate record for matching group-by fields.

Abstract: A computer system includes seveal computing areas which are connected to one another by a number of cables. The cables are necessary to carry information from one computing area to another computing area. The cables can be thought of as the information highway between computing areas. The computer system has a first housing which has a frame. The frame includes an elongated hollow corner post that has an opening along the length of the corner post. The hollow portion of the corner post is used as a cable run.The corner post further comprising an exterior surface having a key way therein. A number of cable guides, each having a key that fits within the key way of said elongated corner post, is attached to the corner post. Each cable guide has a two ends. One of said ends is positioned near the opening in the corner post and the other end of said cable guide is positioned near a computing area when the cable guide is positioned within the key way.

Abstract: A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address.

Abstract: A method, system, and computer program product for accelerated shading of an object surface by bump mapping in tangent space. A tangent space transform module builds a tangent space transform matrix M(p) having elements comprised of normal, tangent, and binormal vector components determined at a surface point on the object surface. The tangent space transform module further transforms shading vectors, such as, lighting and viewing vectors, into a tangent space defined by the tangent space transform matrix and outputs corresponding tangent space shading vectors. A bump mapping module performs vector operations between one or more tangent space shading vectors and a perturbed normal N' in tangent space. A texture memory stores a surface dependent or a surface independent tangent space perturbed normal texture map. The lighting module computes a shading value for the surface point based on the vector operations.

Abstract: A system and method for converting a color uses an extended color space to convert a color from a first color space to a second color space. The extended color space is extended from the second color space. In other words, the extended color space has increased valid component ranges compared with the second color space to accommodate the conversion of any valid colors from the first color space. Subsequent operations on the converted color in the extended color space occur without the presence of conversion artifacts found in many conventional color space converters.

Abstract: A method for concealing errors during transmission of audio data packets. Initially, the fundamental pitch period of a data packet is determined. A value indicating this fundamental pitch period is added as a preamble to the data packet prior to its transmission. When a data packet is received, it is checked for dropped or corrupted data. If there are any errors, the fundamental pitch period is replicated with the data from the previous frame the requisite number of times and substituted in replacement thereof. The audio is then played back so the impact of any errors is perceptually insignificant.

Abstract: A method and apparatus for producing output values corresponding to pixels of an input image. A coordinate translation circuit for is provided for performing coordinate translation from input pixel color components to corresponding texture coordinates. The texture coordinates collectively determine a texture address. The coordinate translation circuit also generates a set of interpolation factors in one embodiment used to resample around the point in texture space defined by the texture address. An interpolation circuit is coupled to the coordinate translation circuit to receive the texture address and the set of interpolation factors. The interpolation circuit uses the texture address and the set of interpolation factors to produce an output value. Typically, the output value represents a multidimensional lookup of the color components interpolated into multidimensional space.

Abstract: A method of displaying an object in a real-time simulation using silhouette load mangement techniques, whereby a minimal number of polygons is used in the display process. Two-dimensional silhouettes are created by taking snapshots of three-dimensional models at various angles of view. These silhouettes are stored in texture memory. The appropriate silhouette is selected for display depending upon the angle from which that object is viewed. As the angle of view changes, a different silhouette is selected for display. Once a threshold, such as the angle of rotation or the distance from the viewer, has been reached, the three-dimensional model is substituted for the silhouette for display.

Abstract: A system and method for managing multiple frame buffers. The system includes multiple frame buffers, and thus reduces the risk of dropped frames. The system controls and bounds render-to-display latency, and provides an application friendly and effective interface to the frame buffers. The system operates by estimating a latency of a frame that is yet to be rendered. The system determines whether the latency is greater than a target latency. If the latency is greater than the target latency, then the system blocks the application that is responsible for rendering the frame before rendering of the frame commences. As a result, render-to-display latency is bounded to the target latency. The system addresses the naming issue by providing the application with access to only the front buffer and the back buffer. In particular, the present system maintains a queue of one or more frame buffers. The newest frame buffer appended to the queue is considered to be the front buffer.