Abstract: A low cost high performance three dimensional (3D) graphics system is disclosed that can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a color television set.The richly featured high performance low cost system is intended to give consumers the chance to interact in real time right inside magnificent virtual 3D worlds to provide a high degree of image realism, excitement and flexibility. An optimum feature set/architecture (including a custom designed graphics/audio coprocessor) provides high quality fast moving 3D images and digital stereo sound for video game play and other graphics applications.

Abstract: A method and apparatus for rendering lightpoints is provided. For the method of the present invention, a programmer creates a series of texture maps. Each texture map approximates the lobe of a lightpoint at a respective distance from the lightpoint. Each texture map includes transparency texture information. This allows the lightpoint to correctly model fog and other atmospheric conditions. The series of texture maps are encoded in a mipmap associated with the lightpoint. During use, a simulation environment renders the lightpoint using a billboarding technique. The billboarding technique keeps the lobe of the lightpoint oriented towards the eye point. The simulation environment dynamically tracks the distance from the lightpoint to the eye point. Each time the distance changes, the simulation environment selects an appropriate texture map from the mipmap. The appropriate texture map is the texture map that correctly depicts the lightpoint at the distance between the eye point and the lightpoint.

Abstract: A method, system, and computer program product are provided for accelerated shading of an object surface by bump mapping in tangent space or object space. A tangent space transform module builds a tangent space transform matrix M(p) having elements comprised of normal, tangent, and binormal vector components determined at a surface point on the object surface. The tangent space transform module further transforms shading vectors, such as, lighting and viewing vectors, into a tangent space defined by the tangent space transform matrix and outputs corresponding tangent space shading vectors. A bump mapping module performs vector operations between one or more tangent space shading vectors and a perturbed normal N' in tangent space. A texture memory stores a surface dependent or a surface independent tangent space perturbed normal texture map. The lighting module computes a shading value for the surface point based on the vector operations.

Abstract: A video frame detector circuit used in synchronizing one video signal with another video signal. The video frame detector of the present invention is able to automatically detect a start of frame portion of any video composite synchronization signal connected to it without requiring programming. The start of frame commences with the least frequent vertical field, or if all fields are equally frequent, a deterministic process is used to promote one of the fields to be the start of the frame. Since the video frame detector circuit of the present invention does not require programming to recognize various video signal formats, it readily adapts to different video signal conditions with little or no manual intervention. The video frame detector contains a number of memory stores for storing previously detected video patterns obtained from a composite synchronization signal. Once a current pattern is ascertained from the composite synchronization signal, it is compared against the stored patterns.

Abstract: A method for creating and maintaining a dual scene graph for the display of a computer generated object. The user creates a user scene graph which has a number of node in a hierarchical organization which represents an object. This user scene graph is organized according to the dictates of the user for ease of human comprehension. The computer system automatically converts this user scene graph into a separate scene graph. The organization of this second scene graph is optimized so that the object can be rendered faster and more efficiently. Thereby, the first scene graph is displayed to the user so that the user can add, delete, or otherwise modify the object. Any changes made to the user scene graph are automatically made to the second scene graph, transparent to the user. The object is rendered for display according to the second scene graph.

Abstract: A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit.

Abstract: A method, system, and computer program product for performing speculative code motion within a sparse partial redundancy elimination (PRE) framework. Speculative code motion (i.e., speculation) refers to the placement of computations by a compiler in positions in the program that results in some paths being executed more efficiently and some being executed less efficiently. A net speed-up is thus achieved when the improved paths are those executed more frequently during the program's execution. Two embodiments for performing speculative code motion within the PRE framework are presented: (1) a conservative speculation method used in the absence of profile data; and (2) a profile-driven speculation method used when profile data are available. In a preferred embodiment, the two methods may be performed within static single assignment PRE (SSAPRE) resulting in better optimized code.

Abstract: A system and method for converting a color uses an extended color space to convert a color from a first color space to a second color space. The extended color space is extended from the second color space. In other words, the extended color space has increased valid component ranges compared with the second color space to accommodate the conversion of any valid colors from the first color space. Subsequent operations on the converted color in the extended color space occur without the presence of conversion artifacts found in many conventional color space converters.

Abstract: A system, method and computer program product for sharing memory between fault-isolated cells of a computer system. A page of memory is exported from an exporting cell to an importing cell by selectively opening a hole in a fire-wall that otherwise fault-isolates the exporting cell and the importing cell. The fire-wall opening permits the importing cell to access a specific page of memory in the exporting cell. Access to other memory cells is still prevented by the fire-wall. When a page of memory is exported, a record of the export is generated in the exporting cell. Export records are used to determine whether a requesting cell is permitted to access a requested page of memory and to terminate memory exports in a controlled fashion. When a page of memory is imported, an import record and a proxy page frame data structure are generated in the importing cell. Import records are used to access pages of memory in other cells and to terminate imports in a controlled fashion.

Abstract: An operation for combining multiple video streams permits combining any number of overlay images and base images regardless of processes performed upon one or more of the images. Specifically, where the base images are dynamically sized and resized to provide a constant frame rate (despite varying frame complexity), the process similarly treats overlay images and even other base images. In the dynamic sizing process, a rendering time is compared to high and low water marks. During dynamic resizing, two double buffering operations and a synchronization operation are performed. After dynamic sizing and resizing, the resulting resized images are combined together, regardless of the frame rate of the individual images. Consequently, multiple video streams at varying frame rates are combined at a constant frame rate.

Abstract: A light distributing removable door assembly (and elements thereof) for a back-lit flat panel display subsystem wherein the subsystem is for direct viewing as a monitor and having overhead projection capability. The removable door assembly provides for back-lighting via a light pipe for direct viewing when installed in the subassembly. When the door assembly is removed, the active matrix LCD is semi-transparent and can be placed over the imaging screen (viewing side down) of an overhead projector such that the LCD color image can be thus projected. The lamps that provide the back-lighting remain within the display subsystem when the door is removed and a unique optical coupling is provided between the lamps and a light pipe within the door. A specialized bi-directional light extraction pattern is used on a light pipe of the removable door to provide effective and uniform light distribution over the LCD image.

Abstract: An interconnection device has a multiplicity of individual arms attached to a carrier board. The carrier board includes vias which go through the board and have a pad on the top and bottom of the board near the via. Attached to each via pad is an arm. The arm is attached so that its free end extends out over the clearance hole in the carrier board. The free end of the arm positioned over the clearance hole includes a surface treatment which allows the free end to make good electrical contact with a mating device. Each of the arms is positioned so that it corresponds to the pads on the device to which it will connect. Each of the arms acts as a cantilevered beam. The arms are deflected. The geometry, material, material temper, and surface plating allow for a very low overall force having to be applied to the interconnection in order to provide good electrical contact between the first module and second module being interconnected. The amount of compliance may be 10 to 12 mils.

Abstract: A method, system, and computer program product provides data visualization which optimizes visualization of and navigation through hierarchies. A partial hierarchy is generated and displayed. The partial hierarchy consists of a number levels at least equal to a predetermined depth and less than a total number of levels included in a corresponding complete hierarchy. Parent nodes in the bottom level of the partial hierarchy have segments of connection lines extending toward child nodes not included in the partial hierarchy. A user is permitted to mark selected nodes or locations in a displayed partial hierarchy. Partial hierarchies are generated and stored in a cache or generated on-the-fly. Each partial hierarchy ends at a progressively deeper level. An interpolator interpolates a partial hierarchy layout by interpolating corresponding nodes in two partial hierarchies. A hierarchy manager manages partial hierarchies in response to requests from a viewer to move a camera to camera positions.

Abstract: An efficient method for width independent antialiasing of point primitives and line primitives in a frame buffer of a graphics computer system. The graphics computer system calculates an integral of an impulse response of a low pass filter. A plurality of values representative of the integral of the impulse response are stored in a look-up table. The plurality of values are indexed with respect to distance. A primitive is rasterized into the frame buffer, wherein the primitive is either a point primitive or a line primitive. The distance of a resulting fragment from the center of the primitive is then calculated. The look-up table is then entered using the distance as an argument, and a corresponding one of the plurality of values is retrieved. This value is used as a blending weight for the fragment. The color of the fragment is then blended into the frame buffer using the one of the plurality of values as the blending weight. In so doing, the primitive is properly antialiased regardless of its width.

Abstract: A door assembly that includes a door that is operable to alternatively expose and cover an opening in the bezel of a computer. The door assembly includes a carriage that slides up and down that pivotally couples to the door. Upon pressing against the lower portion of the door, the door pivots and the carriage and the door automatically slide down such that the door no longer covers the opening in the bezel. When an upward force is applied to the door, the door and the carriage move upward and into the closed position. As the door reaches the opening in the bezel, a spring forces the door against the bezel and into the closed position. The door is easily opened and closed and the door is out of the way when the door is in the open position.

Abstract: A computer implemented method edits a surface by displaying a surface rendered from a polygonal mesh defined by mesh elements, selecting, as an edit mesh element, a mesh element displayed in the surface, determining a set of affected mesh elements from the polygonal mesh wherein each affected mesh element is within a specified vicinity of the edit mesh element, editing the edit mesh element in response to user input, and editing the affected mesh elements based on the edited edit mesh element.

Abstract: A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a .chi. function, zero or more occurences of a .phi. function, and zero or more occurrences of a .mu. function. The .chi. function, .phi. function, and .mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version.

Abstract: A hardware implementation solves for the value of X.sup.Y, where X and Y are real (fixed point or floating point) numbers by using the formula X.sup.Y =exp (log.sub.e (X.sup.Y))=exp(ln(X.sup.Y))=exp(Y*ln(X)). A fixed point representation of X, output from a flip-flop, is used to address a floating point data output from an ln(X) ROM lookup table. The floating point data output is output from a second flip-flop and multiplied by Y in a multiplier to yield a product. The product is output from a third flip-flop to address a fixed point data output from an exp(X) ROM lookup table. The fixed point data output is latched by and output from a third flip-flop. The fixed point data output approximates X.sup.Y, using a minimal amount of die area on the semiconductor and minimal amount of processing power. Also, the present invention can be fully pipelined, such that one calculation can be conducted every cycle and operations can occur simultaneously.

Abstract: An .times.86 based computer system that implements a firmware based boot process without an .times.86 BIOS that supports expansion devices coupled to the computer system, wherein the expansion devices include their own respective BIOS extensions. The computer system includes an .times.86 processor coupled to a volatile memory and a non-volatile memory via a bus. The non-volatile memory includes firmware which when executed by the processor cause the computer system to implement the boot process. The firmware initializes device drivers for the computer system and initializes an application programming interface for the device drivers. The firmware then initializes a compatibility component for interfacing with the device drivers, wherein the compatibility component is operable for translating accesses by a first software application to an .times.86 BIOS into corresponding accesses to the device drivers.

Abstract: A method, system, and computer program product for performing register promotion, that optimizes placement of load and store operations of a computer program within a compiler. Based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location, the system is an approach to register promotion that models the optimization as two separate problems: (1) the partial redundancy elimination (PRE) of loads and (2) the PRE of stores. Both of these problems are solved through a sparse approach to PRE. The static single assignment PRE (SSAPRE) method for eliminating partial redundancy using a sparse SSA representation representations the foundation in eliminating redundancy among memory accesses, enabling the achievement of both computational and live range optimality in register promotion results.