Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

Abstract: A non-volatile memory (NVM) driver includes a function library with native function calls and a hardware abstraction layer for receiving at least one instruction from the function library and providing signals to cause an NVM to execute the at least one instruction. The NVM includes a plurality of sectors, and the NVM driver uses a first portion as an application visible memory, and a second portion for another purpose. The NVM driver maintains the NVM as a circular buffer within the application visible memory. When a native function call is a resizing command, the function library adjusts the circular buffer selectively according to whether the resizing command increases or decreases the application visible memory. When a native function call is a write counter command, the NVM driver selectively creates a new counter object including a counter base and a plurality of increment locations using a next location pointer.

Abstract: An integrated circuit includes an on-chip PLL response measurement capability. The PLL response is determined in terms of PLL bandwidth and PLL peaking. A digital phase offset is inserted to a digital representation of a first clock signal to create a phase step. A phase and frequency detector of a phase-locked loop (PLL) supplies a phase error signal indicative of a difference between the first clock signal and a second clock signal. The elapsed time between the phase step insertion and the first zero crossing of the phase error as the PLL tries to deal with the is used to determine PLL bandwidth. The maximum phase error overshoot resulting from insertion of the digital phase offset is determined for use in determining PLL peaking.

Abstract: In one form, an integrated circuit includes a plurality of electromagnetic fault injection (EMFI) sensors and a security management circuit. Each EMFI sensor includes a sense loop having a conductor around a corresponding portion of logic circuitry whose operation is affected by an electromagnetic pulse, and a detector circuit coupled to the sense loop and having an output for providing a pulse detection signal in response to a pulse of at least a predetermined magnitude. The security management circuit performs a protection operation to secure the integrated circuit in response to an activation of a corresponding pulse detection signal of one of the plurality of EMFI sensors.

Abstract: A method for calibrating a successive-approximation analog-to-digital converter (ADC) includes configuring the successive-approximation ADC in a calibration mode of operation. The method includes, while in the calibration mode of operation: determining a digital code corresponding to a programmable capacitance of the successive-approximation analog-to-digital converter, and storing the digital code corresponding to the programmable capacitance in a storage element of an integrated circuit die including the successive-approximation ADC. The programmable capacitance may be a gain tuning capacitance, a bridge tuning capacitance, an offset capacitance, or a monotonicity tuning capacitance.

Abstract: A system and method of allowing a new device to join an existing network are disclosed. A configuration tool is used to communicate relevant information from the new network device to the gateway in the existing network using a secondary network protocol different from that used by the primary network. For example, in one embodiment, messages are exchanged between the configuration tool and the new device and between the configuration tool and the gateway using BLUETOOTH®. Once all of the pertinent information has been exchanged, the new device is able to securely join the primary network, which may be based on the IEEE802.15.4 standard.

Abstract: A system and method for transmitting packets to a plurality of network devices that cannot be accessed via a single multicast message is disclosed. The system includes a gateway controller that received a multicast request from a client, and creates a plurality of multicast messages based on the number of different security classes. The gateway controller parses the request from the client and identifies all of the desired destination nodes. The gateway controller then identifies the security class that each of these destination nodes belongs to. Based on this, the gateway controller then creates one or more multicast messages, where each multicast message is intended for the destination nodes that belong to a single security class. In certain embodiments, the gateway controller also aggregates the acknowledgments from the destination nodes and forwards this information to the client.

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: A wireless receiver including a front end circuit, an adaptive threshold circuit, and a correlator. The front end circuit converts a wireless signal into a series of digital symbols. The adaptive threshold circuit provides an adaptive correlation threshold that is adapted based on a sync word. The correlator correlates the digital symbols with the sync word using the adaptive correlation threshold. The adaptive correlation threshold may be based on amplitude attenuation of the digital symbols that correspond to transitions of the sync word. The adaptive threshold circuit may be a lookup table that stores different threshold values each corresponding to one of multiple different sync words. Alternatively, the adaptive threshold circuit may be implemented as an evaluation circuit that determines the adaptive correlation threshold based on expected amplitude attenuation of the digital symbols that correspond to transitions of the sync word.

Abstract: A robotic integrated circuit placement system includes a test board comprising a socket for holding an integrated circuit, a tester coupled to the test board, a chip tray having a plurality of slots for storing respective integrated circuits including the integrated circuit, and a robotic arm system. The robotic arm system includes a robotic arm having a stepper motor for controlling a position of an end of the robotic arm, a camera, and a controller coupled to the robotic arm and adapted to operate the robotic arm automatically. The controller performs image processing on images acquired by the camera, and moves the integrated circuit between the chip tray and the socket using the robotic arm in response to the image processing.

Abstract: A robotic arm system includes a robotic arm having at least one stepper motor and operable to move an end of the robotic arm in X-, Y-, and Z-dimensions, a camera attached to the robotic arm, and a controller coupled to the robotic arm and to the camera. During configuration, the controller moves the end of the robotic arm to a reference point to obtain initial reference coordinates and a reference image, and to a target location to obtain initial target coordinates. During operation, the controller moves the robotic arm according to the initial reference coordinates, adjusts a position of the robotic arm to an actual reference location using the camera to determine actual reference coordinates, and moves the robotic arm to an actual target location using the initial target coordinates and a difference between the initial reference coordinates and the actual reference coordinates.

Abstract: A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.

Abstract: A method for operating an ADC includes storing a sampled input charge on a capacitance of a sample-and-hold circuit including a DAC. The sampled input charge is stored using a first reference signal coupled to the DAC and a second signal. The sampled input charge has a value based on a first digital code. The method includes converting a second digital code to an analog signal on the first node using the DAC, the sampled input charge, and the first reference signal. The second digital code is one least-significant bit different from the first digital code. The method includes generating a monotonicity indicator indicating whether an output analog signal of the DAC is monotonic in response to a transition of a digital input of the DAC from the first digital code to the second digital code based on a comparison of the analog signal to the second signal.

Abstract: An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.

Abstract: An integrated circuit including at least one circuit node, multiple duplicate circuit blocks integrated on the integrated circuit in close proximity with each other, each including at least one device that is susceptible to random telegraph noise (RTN), and a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices, such as differential pairs or the like. Each duplicate circuit block may include any number of connections for coupling to corresponding circuit nodes. The swapping may further include chopping in which multiple inputs are swapped with each other while multiple outputs are swapped with each other in consecutive clock cycles.

Abstract: A successive-approximation ADC includes an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion. A gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion. A charge-redistribution DAC includes a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion, a remaining portion of the sampled input charge, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of the third phase. The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.

Abstract: A technique establishes a powered link over a transmission line. The technique includes, after determination of a power level to be provided to a powered device coupled to the transmission line, providing an output signal having a power-saving signal level to the transmission line until detecting an event. The event may be a power-up or a disconnect of the powered device. The technique may further include changing the output signal from the power-saving signal level to the powered-mode output signal level. The technique may include providing the powered-mode output signal level until detecting a disconnect of the powered device. The technique may include providing a second output signal to an additional powered device coupled to an additional transmission line until detecting the event. The technique may include changing the second output signal from the power-saving signal level to a second powered-mode output signal level synchronous with changing the output signal.

Abstract: An integrated circuit includes a digital circuit and an energy management circuit. The digital circuit operates with an internal power supply voltage in synchronism with a clock signal and comprises complementary metal-oxide-semiconductor (CMOS) transistors. The energy management circuit has an input for receiving an external power supply voltage and an output for providing the internal power supply voltage. The energy management circuit is thermally coupled to the digital circuit and sets the internal power supply voltage to a nominal voltage when a temperature of the digital circuit is greater than a boost temperature. The energy management circuit boosts the internal power supply voltage to a boosted voltage greater than the nominal voltage when the temperature of the digital circuit is less than the boost temperature.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.

Abstract: A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.