Abstract: In one example, a system includes: a circuit board; at least one tuner adapted on the circuit board to receive and process a radio frequency (RF) signal to output a downconverted modulated signal; a processor adapted on the circuit board to demodulate the downconverted modulated signal, process the demodulated downconverted signal and output an audio signal; a location on the circuit board to receive a demodulator circuit; and a shunt element adapted on the circuit board to direct the downconverted modulated signal from the at least one tuner to the processor when the system does not include the demodulator circuit.

Abstract: An apparatus includes a radio-frequency (RF) receiver, which includes an automatic gain-control (AGC) circuit to use a gain signal to set a gain of front-end circuitry of the RF receiver. The RF receiver further includes an interference-detection circuit to use a value of the gain signal to detect an interference signal.

Abstract: A wireless locator that facilitates determining a location of a nearby wireless asset including an antenna array with multiple antennas, at least one wireless transceiver that receives a location signal from the nearby wireless asset and that takes multiple samples from the location signal including a set of samples for each antenna, and a processor that compresses the samples to generate location information associated with the nearby wireless asset. The wireless locator may be part of a wireless location system including multiple wireless locators distributed in the area and a central processing system. Various compression methods are disclosed, including averaging of the samples, bit reduction of the samples, converting the samples to corresponding phase values, and combining corresponding samples of multiple sample supplemental sets. Combinations of the various compression methods are also disclosed.

Abstract: Embodiments of improved systems and methods are provided herein to reset all datapath logic within a peripheral slave device having multiple clock domains. An embodiment of the disclosed method includes receiving a reset request from a host clock device to reset the peripheral slave device, synchronizing the received reset request to each peripheral clock domain included within the peripheral slave device, and using the synchronized reset request generated within each peripheral clock domain to reset datapath logic contained within that peripheral clock domain.

Abstract: A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.

Abstract: A power saving wire-free earpiece has a Bluetooth transceiver and a Bluetooth Low Energy (BLE) transceiver. A stream of audio from a remote source is separated into a local audio stream and a stream sent to the BLE transceiver for a remote earpiece. The earpiece is operative in a first and second mode, the first mode enabling the BT transceiver and BLE transceiver, the second mode enabling only the BLE transceiver for receiving remote streams of data. The first and second mode alternate so that the local and remote earpiece have substantially uniform current requirements.

Abstract: In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.

Abstract: In an embodiment, an apparatus includes: a signal pad; a first diode having a first terminal coupled to the signal pad and a second terminal, the first diode having a first polarity; a second diode having a second terminal coupled to the signal pad and a first terminal, the second diode having a second polarity; a first insulated gate bipolar transistor (IGBT) having a first polarity, the first IGBT coupled between the second terminal of the first diode and a reference voltage node; and a second IGBT having the first polarity, the second IGBT coupled between the first terminal of the second diode and the reference voltage node.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

Abstract: A non-volatile memory (NVM) driver includes a function library with native function calls and a hardware abstraction layer for receiving at least one instruction from the function library and providing signals to cause an NVM to execute the at least one instruction. The NVM includes a plurality of sectors, and the NVM driver uses a first portion as an application visible memory, and a second portion for another purpose. The NVM driver maintains the NVM as a circular buffer within the application visible memory. When a native function call is a resizing command, the function library adjusts the circular buffer selectively according to whether the resizing command increases or decreases the application visible memory. When a native function call is a write counter command, the NVM driver selectively creates a new counter object including a counter base and a plurality of increment locations using a next location pointer.

Abstract: An integrated circuit includes an on-chip PLL response measurement capability. The PLL response is determined in terms of PLL bandwidth and PLL peaking. A digital phase offset is inserted to a digital representation of a first clock signal to create a phase step. A phase and frequency detector of a phase-locked loop (PLL) supplies a phase error signal indicative of a difference between the first clock signal and a second clock signal. The elapsed time between the phase step insertion and the first zero crossing of the phase error as the PLL tries to deal with the is used to determine PLL bandwidth. The maximum phase error overshoot resulting from insertion of the digital phase offset is determined for use in determining PLL peaking.

Abstract: In one form, an integrated circuit includes a plurality of electromagnetic fault injection (EMFI) sensors and a security management circuit. Each EMFI sensor includes a sense loop having a conductor around a corresponding portion of logic circuitry whose operation is affected by an electromagnetic pulse, and a detector circuit coupled to the sense loop and having an output for providing a pulse detection signal in response to a pulse of at least a predetermined magnitude. The security management circuit performs a protection operation to secure the integrated circuit in response to an activation of a corresponding pulse detection signal of one of the plurality of EMFI sensors.

Abstract: A system and method of allowing a new device to join an existing network are disclosed. A configuration tool is used to communicate relevant information from the new network device to the gateway in the existing network using a secondary network protocol different from that used by the primary network. For example, in one embodiment, messages are exchanged between the configuration tool and the new device and between the configuration tool and the gateway using BLUETOOTH®. Once all of the pertinent information has been exchanged, the new device is able to securely join the primary network, which may be based on the IEEE802.15.4 standard.

Abstract: A method for calibrating a successive-approximation analog-to-digital converter (ADC) includes configuring the successive-approximation ADC in a calibration mode of operation. The method includes, while in the calibration mode of operation: determining a digital code corresponding to a programmable capacitance of the successive-approximation analog-to-digital converter, and storing the digital code corresponding to the programmable capacitance in a storage element of an integrated circuit die including the successive-approximation ADC. The programmable capacitance may be a gain tuning capacitance, a bridge tuning capacitance, an offset capacitance, or a monotonicity tuning capacitance.

Abstract: A system and method for transmitting packets to a plurality of network devices that cannot be accessed via a single multicast message is disclosed. The system includes a gateway controller that received a multicast request from a client, and creates a plurality of multicast messages based on the number of different security classes. The gateway controller parses the request from the client and identifies all of the desired destination nodes. The gateway controller then identifies the security class that each of these destination nodes belongs to. Based on this, the gateway controller then creates one or more multicast messages, where each multicast message is intended for the destination nodes that belong to a single security class. In certain embodiments, the gateway controller also aggregates the acknowledgments from the destination nodes and forwards this information to the client.

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: A wireless receiver including a front end circuit, an adaptive threshold circuit, and a correlator. The front end circuit converts a wireless signal into a series of digital symbols. The adaptive threshold circuit provides an adaptive correlation threshold that is adapted based on a sync word. The correlator correlates the digital symbols with the sync word using the adaptive correlation threshold. The adaptive correlation threshold may be based on amplitude attenuation of the digital symbols that correspond to transitions of the sync word. The adaptive threshold circuit may be a lookup table that stores different threshold values each corresponding to one of multiple different sync words. Alternatively, the adaptive threshold circuit may be implemented as an evaluation circuit that determines the adaptive correlation threshold based on expected amplitude attenuation of the digital symbols that correspond to transitions of the sync word.

Abstract: A robotic integrated circuit placement system includes a test board comprising a socket for holding an integrated circuit, a tester coupled to the test board, a chip tray having a plurality of slots for storing respective integrated circuits including the integrated circuit, and a robotic arm system. The robotic arm system includes a robotic arm having a stepper motor for controlling a position of an end of the robotic arm, a camera, and a controller coupled to the robotic arm and adapted to operate the robotic arm automatically. The controller performs image processing on images acquired by the camera, and moves the integrated circuit between the chip tray and the socket using the robotic arm in response to the image processing.

Abstract: A robotic arm system includes a robotic arm having at least one stepper motor and operable to move an end of the robotic arm in X-, Y-, and Z-dimensions, a camera attached to the robotic arm, and a controller coupled to the robotic arm and to the camera. During configuration, the controller moves the end of the robotic arm to a reference point to obtain initial reference coordinates and a reference image, and to a target location to obtain initial target coordinates. During operation, the controller moves the robotic arm according to the initial reference coordinates, adjusts a position of the robotic arm to an actual reference location using the camera to determine actual reference coordinates, and moves the robotic arm to an actual target location using the initial target coordinates and a difference between the initial reference coordinates and the actual reference coordinates.