Abstract: An apparatus and method for encrypting messages from a first node splits the message into a plurality of message units, each of which is encrypted. The encrypted message units are split into path units, each of which is directed to a different route path to a destination node. At the destination node, the path units are received and reassembled into encrypted message units, which are decrypted into message fragments and concatenated to form a message corresponding to the original one sent.

Abstract: In one embodiment, an apparatus includes first and second tuners to receive and process a radio frequency (RF) signal and output a first and second plurality of frequency domain sub-carriers. The apparatus may further include a combiner circuit to combine a first plurality of demodulated frequency domain sub-carriers and a second plurality of demodulated frequency domain sub-carriers into a plurality of combined frequency domain sub-carriers, and an output circuit coupled to the combiner circuit. In a first mode, the output circuit is to embed a format indicator with each of the plurality of combined frequency domain sub-carriers to indicate a frequency domain format, and to output the plurality of combined frequency domain sub-carriers with the embedded format indicator to a downstream processing circuit for channel decoding.

Abstract: In one embodiment, an apparatus includes: an antenna switch to receive a first radio frequency (RF) signal from a first antenna and a second RF signal from a second antenna and controllable to output a selected one of the first and second RF signals; an RF circuit to receive and process the first and second RF signals; at least one mixer to downconvert the first and second RF signals to first and second baseband signals; and an antenna diversity control circuit to receive sub-symbol portions of a first plurality of symbols of the first baseband signal and sub-symbol portions of a second plurality of symbols of the second baseband signal, and control the antenna switch to output one of the first and second RF signals, based at least in part on one or more of the sub-symbol portions of the first and second pluralities of symbols.

Abstract: An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

Abstract: A power saving receiver has a controller which is operative to remove power from the receiver when a threshold is exceeded during reception of a packet. The threshold level is formed by comparison of any of: signal energy of unoccupied subcarriers less the signal energy in occupied subcarriers; signal energy in a first range of occupied subcarriers compared to signal energy in a different range of occupied subcarriers; error vector magnitude from a first set of subcarriers to a second set of subcarriers in a different spectral region of the channel; cyclic prefix cross-correlation, or common phase error increase.

Abstract: Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

Abstract: A system and method of downloading firmware into an embedded device while maintaining the integrity and confidentiality of the firmware is disclosed. In one embodiment, the process comprises four phases. In the first phase, unauthenticated content is written into the memory of the embedded device. In the second phase, this content is verified. In the third step, a secure connection is established between the host and the embedded device. In the fourth step, the firmware is loaded into the embedded device using this secure connection. The firmware is encrypted as it is transferred from the host to the embedded device and is never accessible outside of the embedded device.

Abstract: Systems and methods are provided that may be implemented to configure and/or reconfigure device operating modes based on relative position of a wireless transmitter to a wireless receiver that is receiving a wireless radio frequency (RF) signal transmitted from the wireless transmitting device, or vice-versa. The relative position of a wireless transmitter to a wireless receiver may be determined using any suitable technique, e.g., using Time Difference of Arrival (TDOA) of a signal received at separate antenna elements of an antenna array of the wireless receiver, using Angle of Arrival (AoA) of a signal received at an antenna array of the wireless receiver, using measured received signal strength (e.g., received signal strength indicator (RSSI) or received signal decibel-milliwatts (dBm)) of a signal received at different antenna elements of an antenna array of the wireless receiver, using Angle of Departure (AoD) of a signal transmitted from an antenna array of the wireless transmitter, etc.

Abstract: A system and method for optimizing battery life in Bluetooth low power nodes without appreciably affecting latency is disclosed. The low power node may vary its PollTimeout value based on certain criteria, including time of day, ambient conditions or input from other devices. In this way, power consumption is minimized during those times when latency is not anticipated to be problematic, while latency is reduced during other times. In another embodiment, the low power node may save preconstructed messages before going into a low power or sleep mode to minimize the time required to transmit those messages.

Abstract: In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.

Abstract: A receiver signal path includes a programmable flat gain stage configured to provide an amplified differential pair of signals based on a first frequency response having a selectable flat gain and a differential input pair of signals received on an input differential pair of nodes. The receiver signal path includes a peaking gain stage configured to generate a second amplified differential pair of signals based on the amplified differential pair of signals according to a second frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency of the peaking gain stage. The programmable flat gain stage and the peaking gain stage are configured as a variable peaking gain stage. The selectable flat gain is selectively programmed based on a predetermined power consumption of a receiver path.

Abstract: A sine to square wave converter circuit receives a sine wave signal and supplies a first square wave signal having a first frequency. A 2× clock multiplier circuit multiplies the first square wave signal and supplies a second square wave signal with a second frequency that is twice the first frequency. A first storage element that is clocked by the second square wave signal stores a delayed version of the first square wave signal and supplies an even-odd signal. A second storage element that is clocked by the second square wave signal receives the even-odd signal and supplies an odd-even signal. A duty cycle correction circuit adjusts the threshold of the sine to square wave converter based on a difference in duty pulse widths between the even-odd signal and the odd-even signal.

Abstract: An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.

Abstract: A technique for receiving a DC or low frequency input signal using a chopper-stabilized amplifier includes chopping an input signal using a chopper clock signal to generate a chopped input signal. The input signal has a first voltage range and the chopper clock signal has a second voltage range. The chopper clock signal has peak-to-peak voltage over a period of the chopper clock signal. The peak-to-peak voltage is less than the first voltage range and is less than the second voltage range. A frequency of the input signal is at least an order of magnitude less than a frequency of the chopper clock signal. The second voltage range may be greater than or equal to the first voltage range. The technique may include generating a bias signal based on a voltage reference signal and an output signal having the first voltage range.

Abstract: A receiver signal path includes a high pass filter that centers a received differential pair of signals around a common mode voltage to generate a centered received differential pair of signals. The receiver signal path includes a demodulator that removes a carrier signal from the centered received differential pair of signals to generate a demodulated signal and generates a logic signal based on the demodulated signal and a predetermined threshold signal. The demodulator includes a differential stage including an extremum selector circuit that generates the demodulated signal based on the centered received differential pair of signals. The demodulated signal corresponds to a mean level of the rectified version of the centered received differential pair of signals. The differential stage includes a second circuit that provides the reference signal based on the predetermined threshold signal. The logic signal is based on a comparison of the demodulated signal to the reference signal.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: In an embodiment, an apparatus includes: a modulator to modulate a first packet according to rate control information; a physical circuit to transmit the modulated first packet according to power control information; and a dynamic adaptation circuit, for the first packet, to provide the rate control information and the power control information of a first modulation and power pair stored in a first energy map.

Abstract: A system and method for efficiently creating multicast groups is disclosed. The system includes a gateway controller, that receives a multicast request from a client. The gateway controller parses the request from the client and identifies the set of the desired destination nodes. The gateway controller then determines whether an existing multicast group matches this set. If not, the gateway controller creates a new multicast group, preferably by modifying an existing multicast group by adding new destination nodes to that group. This is an efficient way to create multicast groups, as it increases the number of nodes reacting simultaneously to multicast messages when creating multicast groups, and minimizes the number of messages that are required to synchronize the nodes to the new multicast group.

Abstract: A power transfer device includes a first power supply node, a second power supply node, and an oscillator circuit configured to convert an input DC signal across the first power supply node and the second power supply node into an AC signal on a differential pair of nodes comprising a first node and a second node in response to a control signal. The oscillator circuit includes a regulated power supply node and an active shunt regulator circuit configured to clamp a peak voltage level across the regulated power supply node and the second power supply node to a clamped voltage level. The clamped voltage level is linearly related to a first voltage level on the first power supply node.

Abstract: An apparatus includes a radio frequency (RF) circuit to transmit or receive RF signals, and a partitioned antenna structure. The partitioned antenna structure includes a first portion of a resonator and a first portion of a radiator. The first portion of the resonator comprises less than an entire resonator. The first portion of the radiator comprises less than an entire radiator.