Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

Abstract: A system and method of allowing a new device to join an existing network are disclosed. The new device comprises a non-RF-based transmitter, such as a light, a speaker or haptic generator, which emits a sequence that can be received by a facilitator device that is already part of the network. The sequence contains the device specific information associated with the new device. This facilitator device may be a mobile phone, a tablet or other component. The facilitator device then provides this device specific information to the gateway. The gateway then uses this device specific information as it performs a joining process with the new device.

Abstract: Embodiments include cryptographic circuits having isolated operation with respect to embedded sensor operations to mitigate side-channel attacks. A cryptographic circuit, a sensor, and an analog-to-digital converter (ADC) circuit are integrated into an integrated circuit along with a cryptographic circuit. A sensed signal is output with the sensor, and the sensed signal is converted to digital data using the ADC circuit. Further, cryptographic data is generated using one or more secret keys and the cryptographic circuit. The generation of the cryptographic data has isolated operation with respect to the operation of the sensor and the ADC circuit. The isolated operation mitigates side-channel attacks. The isolated operation can be achieved using power supply, clock, and/or reset circuits for the cryptographic circuit that are electrically isolated from similar circuits for the sensor and ADC circuit. The isolated operation can also be achieved using time-division multiplex operations.

Abstract: A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Abstract: A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Abstract: In one embodiment, an apparatus includes: a bias circuit having a replica circuit, the bias circuit to generate an oscillator current that is proportional to a variation of the replica circuit; an oscillator circuit coupled to the bias circuit to receive the oscillator current and generate a plurality of signals using the oscillator current; and a waveform shaper circuit coupled to the oscillator circuit to receive the plurality of signals and generate at least one clock signal from the plurality of signals.

Abstract: An integrated circuit includes a digital circuit and an energy management circuit. The digital circuit operates with an internal power supply voltage in synchronism with a clock signal and comprises complementary metal-oxide-semiconductor (CMOS) transistors. The energy management circuit has an input for receiving an external power supply voltage and an output for providing the internal power supply voltage. The energy management circuit is thermally coupled to the digital circuit and sets the internal power supply voltage to a nominal voltage when a temperature of the digital circuit is greater than a boost temperature. The energy management circuit boosts the internal power supply voltage to a boosted voltage greater than the nominal voltage when the temperature of the digital circuit is less than the boost temperature.

Abstract: A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.

Abstract: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.

Abstract: A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

Abstract: An integrated circuit includes an integrated circuit interface, a wireless communications circuit, a selection circuit, and a control circuit. The integrated circuit interface includes a plurality of power supply input terminals, a plurality of power delivery terminals, and an energy harvest output terminal. The wireless communications circuit is configured to harvest energy received in a wireless communications signal and to provide harvested energy to the energy harvest output terminal. The selection circuit is coupled to the integrated circuit interface and is configured to selectively provide power to the plurality of power delivery terminals based on power received from the plurality of power supply input terminals in response to a control signal. The control circuit is configured to generate the control signal based on a first level of the harvested energy, any signals received on the plurality of power supply input terminals, and predetermined rules.

Abstract: In one example, a system includes: a circuit board; at least one tuner adapted on the circuit board to receive and process a radio frequency (RF) signal to output a downconverted modulated signal; a processor adapted on the circuit board to demodulate the downconverted modulated signal, process the demodulated downconverted signal and output an audio signal; a location on the circuit board to receive a demodulator circuit; and a shunt element adapted on the circuit board to direct the downconverted modulated signal from the at least one tuner to the processor when the system does not include the demodulator circuit.

Abstract: An apparatus includes a radio-frequency (RF) receiver, which includes an automatic gain-control (AGC) circuit to use a gain signal to set a gain of front-end circuitry of the RF receiver. The RF receiver further includes an interference-detection circuit to use a value of the gain signal to detect an interference signal.

Abstract: A wireless locator that facilitates determining a location of a nearby wireless asset including an antenna array with multiple antennas, at least one wireless transceiver that receives a location signal from the nearby wireless asset and that takes multiple samples from the location signal including a set of samples for each antenna, and a processor that compresses the samples to generate location information associated with the nearby wireless asset. The wireless locator may be part of a wireless location system including multiple wireless locators distributed in the area and a central processing system. Various compression methods are disclosed, including averaging of the samples, bit reduction of the samples, converting the samples to corresponding phase values, and combining corresponding samples of multiple sample supplemental sets. Combinations of the various compression methods are also disclosed.

Abstract: A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.

Abstract: Embodiments of improved systems and methods are provided herein to reset all datapath logic within a peripheral slave device having multiple clock domains. An embodiment of the disclosed method includes receiving a reset request from a host clock device to reset the peripheral slave device, synchronizing the received reset request to each peripheral clock domain included within the peripheral slave device, and using the synchronized reset request generated within each peripheral clock domain to reset datapath logic contained within that peripheral clock domain.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: A power saving wire-free earpiece has a Bluetooth transceiver and a Bluetooth Low Energy (BLE) transceiver. A stream of audio from a remote source is separated into a local audio stream and a stream sent to the BLE transceiver for a remote earpiece. The earpiece is operative in a first and second mode, the first mode enabling the BT transceiver and BLE transceiver, the second mode enabling only the BLE transceiver for receiving remote streams of data. The first and second mode alternate so that the local and remote earpiece have substantially uniform current requirements.

Abstract: In an embodiment, an apparatus includes: a signal pad; a first diode having a first terminal coupled to the signal pad and a second terminal, the first diode having a first polarity; a second diode having a second terminal coupled to the signal pad and a first terminal, the second diode having a second polarity; a first insulated gate bipolar transistor (IGBT) having a first polarity, the first IGBT coupled between the second terminal of the first diode and a reference voltage node; and a second IGBT having the first polarity, the second IGBT coupled between the first terminal of the second diode and the reference voltage node.

Abstract: In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.