Abstract: A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.

Abstract: A method for operating an ADC includes storing a sampled input charge on a capacitance of a sample-and-hold circuit including a DAC. The sampled input charge is stored using a first reference signal coupled to the DAC and a second signal. The sampled input charge has a value based on a first digital code. The method includes converting a second digital code to an analog signal on the first node using the DAC, the sampled input charge, and the first reference signal. The second digital code is one least-significant bit different from the first digital code. The method includes generating a monotonicity indicator indicating whether an output analog signal of the DAC is monotonic in response to a transition of a digital input of the DAC from the first digital code to the second digital code based on a comparison of the analog signal to the second signal.

Abstract: A successive-approximation ADC includes an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion. A gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion. A charge-redistribution DAC includes a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion, a remaining portion of the sampled input charge, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of the third phase. The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.

Abstract: An integrated circuit including at least one circuit node, multiple duplicate circuit blocks integrated on the integrated circuit in close proximity with each other, each including at least one device that is susceptible to random telegraph noise (RTN), and a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices, such as differential pairs or the like. Each duplicate circuit block may include any number of connections for coupling to corresponding circuit nodes. The swapping may further include chopping in which multiple inputs are swapped with each other while multiple outputs are swapped with each other in consecutive clock cycles.

Abstract: An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.

Abstract: A technique establishes a powered link over a transmission line. The technique includes, after determination of a power level to be provided to a powered device coupled to the transmission line, providing an output signal having a power-saving signal level to the transmission line until detecting an event. The event may be a power-up or a disconnect of the powered device. The technique may further include changing the output signal from the power-saving signal level to the powered-mode output signal level. The technique may include providing the powered-mode output signal level until detecting a disconnect of the powered device. The technique may include providing a second output signal to an additional powered device coupled to an additional transmission line until detecting the event. The technique may include changing the second output signal from the power-saving signal level to a second powered-mode output signal level synchronous with changing the output signal.

Abstract: An integrated circuit includes a digital circuit and an energy management circuit. The digital circuit operates with an internal power supply voltage in synchronism with a clock signal and comprises complementary metal-oxide-semiconductor (CMOS) transistors. The energy management circuit has an input for receiving an external power supply voltage and an output for providing the internal power supply voltage. The energy management circuit is thermally coupled to the digital circuit and sets the internal power supply voltage to a nominal voltage when a temperature of the digital circuit is greater than a boost temperature. The energy management circuit boosts the internal power supply voltage to a boosted voltage greater than the nominal voltage when the temperature of the digital circuit is less than the boost temperature.

Abstract: A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.

Abstract: A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

Abstract: A bitstream modifier is operative on a packet which uses repetition coding. The bitstream modifier increases randomness of the data in a deterministic manner such that spectral spurs from repetition coding are greatly reduced, thereby providing greater available transmit power. In another example of the invention, baseband samples of a header and/or payload for a Bluetooth packet are modified by a canonical sequence with a low slew rate for data such that the variations in frequency may be tracked by a receiver and the transmitted spectral spurs reduced.

Abstract: A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.

Abstract: A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.

Abstract: A communications system has a low power connectivity processor and a high performance applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

Abstract: Improved clock gating cells and related methods are provided. The clock gating cells include a first mutually exclusive element (ME1), a first inverter and a second mutually exclusive element (ME2). ME1 receives a clock input and an enable signal, which is asynchronous to the clock input, and outputs the enable signal based on a timing relationship between the clock input and the enable signal. The first inverter receives the enable signal output from ME1 and provides an inverted enable signal to ME2. ME2 receives the clock input and the inverted enable signal, and provides a clock output based on a timing relationship between the clock input and the inverted enable signal. Together, ME1 and ME2 resolve meta-stability and eliminate glitches in the clock output by preventing rising and falling edges of the enable signal from passing through the mutually exclusive elements during active phases of the clock input.

Abstract: An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes an analog-to-digital converter (ADC) to convert an analog input signal to a digital output signal in response to an ADC clock signal. The RF receiver further includes a frequency generator to selectively provide either a clock signal to be provided as the ADC clock signal or a signal to be used for in-phase-quadrature (IQ) calibration of the RF receiver.

Abstract: A method for calibrating an isolator product includes generating a differential pair of signals on a differential pair of nodes at an input of a demodulator circuit of a receiver signal path of a first integrated circuit die of the isolator product based on a received differential pair of signals. The method includes generating a diagnostic output signal having a level corresponding to an average amplitude of the differential pair of signals. The method includes driving the diagnostic output signal to an output terminal of the isolator product. The method may include transmitting a diagnostic signal using a carrier signal having a frequency by a second integrated circuit die via an isolation channel. The method may include, during the transmitting, sweeping the frequency of the carrier signal across a frequency band. The method may include, during the sweeping, capturing the diagnostic output signal via the output terminal.

Abstract: A continuous-time (CT) delta-sigma modulator (DSM) based analog to digital converter (ADC) in a radio receive chain supports a wide range of data rates in a power efficient way in a small die area. The ADC utilizes a 2nd order loop-filter with a single-amplifier loop-filter topology using a two stage Miller amplifier with a feed forward path and a push-pull output stage. High bandwidth operations utilize a “negative-R” compensation scheme at the amplifier input. Negative-R assistance is disabled for low data rate applications. With the negative-R assistance disabled, loop-filter resistor values are increased, instead of only the loop filter capacitor values to scale the noise transfer function (NTF), thereby limiting the capacitor area needed and enabling lower power operation. The NTF zero location is programmable allowing the NTF zero to be located near the intermediate frequency for different bandwidths to reduce the DSM quantization noise contribution for narrow-band (low data rate) applications.

Abstract: An apparatus controls a high-power drive device external to a package of a gate driver circuit. A first circuit charges the control node over a first length of time in response to a first signal through the first node indicating an absence of a fault condition and a first level of a control signal. A second circuit discharges the control node over a second length of time in response to a second signal through the second node indicating the absence of the fault condition and a second level of a control signal. A third circuit includes a current amplifier and is configured as a soft shutdown path to discharge the control node over a third length of time in response to the first signal through the first node indicating a presence of the fault condition. The third length of time is different from the second length of time.

Abstract: A method for generating a clock signal includes selecting a primary reference clock signal or a secondary reference clock signal as a reference clock signal for a phase-locked loop configured to generate an output clock signal. The method includes generating an indication of whether a failure of the reference clock signal has occurred by monitoring the secondary reference clock signal and a plurality of additional clock signals using the reference clock signal. The failure is determined based on whether a gross failure of the reference clock signal has occurred and if the gross failure has not occurred, further based on whether a quality failure of the reference clock signal has occurred.