Abstract: In one aspect, an apparatus includes: a fast Fourier transform (FFT) engine to receive orthogonal frequency division multiplexing (OFDM) samples of one or more OFDM symbols and convert the one or more OFDM samples into a plurality of frequency domain carriers; and a tone cancellation circuit coupled to the FFT engine to receive the one or more OFDM samples and generate a plurality of frequency carriers for the one or more OFDM samples, identify a highest magnitude frequency carrier of the plurality of frequency carriers, and remove tone interference from the OFDM samples based at least in part on the highest magnitude frequency carrier.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: In one example, an apparatus includes: a radio frequency (RF) receiver to receive an RF signal; a media access control (MAC) circuit to receive data and output MAC-processed data according to a clock signal that is phase delayed with respect to a source clock signal when the RF receiver is active; and an interference mitigation circuit to receive the MAC-processed data and provide the MAC-processed data to a physical circuit resynchronized to the source clock signal.

Abstract: In an embodiment, an apparatus includes a transceiver with a receiver signal processing path and a transmitter signal processing path. The receiver signal processing path is to receive and process a message. The apparatus further includes a controller coupled to the transceiver to obtain information regarding the message and to determine, based at least in part on the information, a transmit power level for a next message to be sent from the transceiver according to a machine learning model.

Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

Abstract: A system and method for one-way ranging is disclosed. The system comprises a transmitter, also referred to as a tag, transmitting a packet having a sounding sequence. The receiver, also referred to as the locator, receives the sounding sequence. The receiver measures and saves the phase at a plurality of points in time. The sounding sequence has two frequencies, which are additive inverses of one another. A discrete Fourier transform is performed on the plurality of phase measurements to determine the phase of each of the two frequencies. The difference between these two frequencies is related to the time that the packet traveled. Additionally, a calibration of the transmit path and/or receive path may be performed to improve the accuracy of the results.

Abstract: A system and method for remotely monitoring and analyzing devices on a wireless network, such as a ZIGBEE® network, is disclosed. The devices store event logs in a memory device whenever certain events occurs. These event logs are transmitted to a gateway device. The gateway device may operate in standalone mode or in network coprocessor (NCP) mode. The gateway device may then decode the event logs into a human readable output. This human readable output may then be uploaded to a server in the cloud, where further analysis of the human readable output may be performed. This information may then be retrieved by remote devices, such as smart phones. In other modes, the event logs are uploaded to the server in the cloud and the decoding is performed in the cloud.

Abstract: In one form, an integrated circuit includes a plurality of electromagnetic fault injection (EMFI) sensors and a security management circuit. Each EMFI sensor includes a sense loop having a conductor around a corresponding portion of logic circuitry whose operation is affected by an electromagnetic pulse, and a detector circuit coupled to the sense loop and having an output for providing a pulse detection signal in response to a pulse of at least a predetermined magnitude. The security management circuit performs a protection operation to secure the integrated circuit in response to an activation of a corresponding pulse detection signal of one of the plurality of EMFI sensors.

Abstract: A system and method for detecting and receiving packets that are transmitted over a network that utilizes a plurality of channels is disclosed. The system includes a radio circuit, which can be configured to receive packets over a plurality of channels, a processing unit, and a memory in communication with the processing unit. The processing unit loads a set of operating parameters in the radio circuit, which enables the radio circuit to detect and receive packets on a particular channel. If a preamble is not detected within a predetermined time period, the system hops to a different channel by loading a second set of operating parameters in the radio circuit. This process can be repeated for an arbitrary number of channels.

Abstract: A device and method for improving the accuracy of angle of arrival and departure computations is disclosed. The device and method rely on manipulation of the antenna switching pattern to achieve an improved calculation of arrival angle. In one embodiment, the device calculates an estimate angle of arrival using conventional methods. The device then determines which of a plurality of different antenna switching pattern yields the more accurate results at this estimated angle of arrival. The AoA measurement is then repeated using the preferred antenna switching pattern. In another embodiment, the device captures the amplitude and/or phase of the signal from each antenna element. The device then sorts these antenna elements and defines a preferred antenna switching pattern based on the sort list. The AoA measurement is then performed using the preferred antenna switching pattern. In another embodiment, neural networks may be utilized to determine the preferred antenna switching pattern.

Abstract: A voltage reference circuit that can operate in a large supply voltage range with high PSRR, that dissipates low-power for a given output noise, and that has a low temperature-coefficient (TC) across a wide-temperature range. The voltage reference circuit does not require any calibration for low TC and high PSRR, occupies a relatively small circuit area, may be used without additional supply filtering in noisy or high-ripple supply environments, and is more robust against device mismatch effects particularly compared to designs based on sub-threshold operations. The voltage reference circuit is a special form of constant transconductance circuit that uses current mirror ratios that are chosen to achieve high PSSR and low noise properties. The device saturation voltage may be chosen so that flat temperature characteristics may be achieved.

Abstract: A device and method for improving the accuracy of angle of arrival and departure computations is disclosed. The device and method rely on manipulation of the antenna switching pattern to achieve an improved calculation of arrival angle. In one embodiment, the device calculates an estimate angle of arrival using conventional methods. The device then determines which of a plurality of different antenna switching pattern yields the more accurate results at this estimated angle of arrival. The AoA measurement is then repeated using the preferred antenna switching pattern. In another embodiment, the device captures the amplitude and/or phase of the signal from each antenna element. The device then sorts these antenna elements and defines a preferred antenna switching pattern based on the sort list. The AoA measurement is then performed using the preferred antenna switching pattern. In another embodiment, neural networks may be utilized to determine the preferred antenna switching pattern.

Abstract: A wireless local area network (WLAN) station receiver has a center frequency offset (CFO) estimator and an CFO table with an association between a CFO value from a recently received access point packet for which the station is associated according to 802.11. The receiver performs a comparison between the CFO estimate of the received packet and the CFO value from the CFO database, and powers the receiver down if the comparison exceeds a threshold. The threshold may be an absolute value in parts per million, or may include a time drift compensation component.

Abstract: The present invention relates to a method and apparatus for reducing power consumption in a receiver of a time slotted communication system. An RF front end has power applied after the start of a preamble or after the start of a header, or upon the start of a packet payload based on connection status, signal level, and interference level. Where the signal level is constant, the communication system is in a connected state, and the interference level is low, the system bypasses packet header destination address matching, or optionally, uses only the least significant bits of the header destination address for matching purposes.

Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

Abstract: A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

Abstract: Systems and methods are provided that may be implemented to use angle of arrival (AoA) of a signal transmitted between two Bluetooth Low Energy (BLE) wireless devices to initially authenticate a connection between the two BLE devices. In one example, bonding or pairing with a first BLE device may be restricted to only those other BLE devices having an antenna currently positioned to transmit a signal to the first BLE device from an allowed direction and within a predefined permitted range of AoA relative to the first BLE device.

Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.

Abstract: A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.